Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	592771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3342900

1

T5

6

T6

18

T7

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	968041	1			T6	16		T7	25		T4	48
values[0x0]	1365590	1			T5	16		T6	19		T7	13
values[0x1]	1602040	1			T5	11		T6	14		T7	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	329600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3606071

1

T5

10

T6

23

T7

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14820	1			T1	12		T2	369		T21	1
valid_sources[0x01]	17208	1			T1	20		T18	2		T2	473
valid_sources[0x02]	16278	1			T1	12		T2	395		T20	2
valid_sources[0x03]	16083	1			T4	1		T1	10		T2	255
valid_sources[0x04]	14421	1			T1	7		T2	458		T30	1
valid_sources[0x05]	15147	1			T1	19		T2	414		T31	3
valid_sources[0x06]	14849	1			T1	14		T2	428		T72	2
valid_sources[0x07]	15696	1			T6	1		T26	4		T1	11
valid_sources[0x08]	15017	1			T4	2		T1	9		T2	381
valid_sources[0x09]	16041	1			T6	2		T1	3		T2	463
valid_sources[0x0a]	14590	1			T1	3		T2	401		T31	5
valid_sources[0x0b]	14932	1			T1	9		T2	393		T34	4
valid_sources[0x0c]	15874	1			T1	19		T17	1		T2	377
valid_sources[0x0d]	15206	1			T4	2		T1	6		T2	412
valid_sources[0x0e]	13623	1			T6	1		T4	2		T1	7
valid_sources[0x0f]	14869	1			T6	1		T26	3		T1	7
valid_sources[0x10]	14908	1			T1	12		T2	425		T30	2
valid_sources[0x11]	16024	1			T1	10		T2	400		T31	7
valid_sources[0x12]	15194	1			T6	1		T24	1		T1	7
valid_sources[0x13]	16297	1			T4	8		T1	17		T18	12
valid_sources[0x14]	15810	1			T4	1		T1	10		T2	438
valid_sources[0x15]	14915	1			T4	4		T1	10		T2	396
valid_sources[0x16]	15621	1			T6	1		T1	14		T2	420
valid_sources[0x17]	14733	1			T4	3		T1	1		T2	347
valid_sources[0x18]	14972	1			T4	1		T1	19		T2	343
valid_sources[0x19]	16267	1			T6	1		T1	11		T2	367
valid_sources[0x1a]	18236	1			T5	1		T1	16		T2	347
valid_sources[0x1b]	15130	1			T4	1		T1	6		T2	309
valid_sources[0x1c]	14656	1			T4	1		T24	1		T1	5
valid_sources[0x1d]	14703	1			T5	1		T26	1		T1	16
valid_sources[0x1e]	17123	1			T1	7		T2	410		T31	7
valid_sources[0x1f]	16112	1			T4	1		T1	10		T2	395
valid_sources[0x20]	14212	1			T1	20		T2	424		T31	6
valid_sources[0x21]	15444	1			T1	17		T17	2		T2	426
valid_sources[0x22]	15141	1			T1	26		T2	429		T30	1
valid_sources[0x23]	14377	1			T1	14		T2	402		T31	2
valid_sources[0x24]	16159	1			T1	3		T2	422		T31	2
valid_sources[0x25]	14058	1			T7	8		T1	8		T2	354
valid_sources[0x26]	15348	1			T1	10		T2	533		T21	1
valid_sources[0x27]	16456	1			T4	1		T26	7		T1	12
valid_sources[0x28]	16131	1			T1	5		T2	377		T34	1
valid_sources[0x29]	15493	1			T1	4		T2	443		T31	3
valid_sources[0x2a]	15288	1			T1	3		T2	352		T31	4
valid_sources[0x2b]	15496	1			T26	1		T1	4		T2	384
valid_sources[0x2c]	15846	1			T1	4		T2	418		T71	1
valid_sources[0x2d]	14601	1			T7	4		T26	2		T1	16
valid_sources[0x2e]	14277	1			T24	1		T1	12		T2	286
valid_sources[0x2f]	16501	1			T4	4		T1	17		T2	354
valid_sources[0x30]	14967	1			T1	18		T2	304		T21	2
valid_sources[0x31]	15067	1			T1	19		T2	408		T72	1
valid_sources[0x32]	14410	1			T6	1		T1	7		T2	376
valid_sources[0x33]	14247	1			T1	7		T2	382		T31	3
valid_sources[0x34]	14760	1			T1	11		T2	341		T31	5
valid_sources[0x35]	15614	1			T1	9		T17	1		T2	370
valid_sources[0x36]	16129	1			T1	11		T2	521		T72	2
valid_sources[0x37]	16880	1			T6	1		T1	11		T2	445
valid_sources[0x38]	14626	1			T26	5		T1	11		T2	351
valid_sources[0x39]	15665	1			T1	5		T2	441		T23	25
valid_sources[0x3a]	15372	1			T1	9		T2	344		T31	6
valid_sources[0x3b]	14537	1			T6	1		T24	1		T1	10
valid_sources[0x3c]	15106	1			T1	5		T2	389		T30	1
valid_sources[0x3d]	14461	1			T1	2		T2	417		T30	3
valid_sources[0x3e]	15629	1			T26	2		T1	6		T2	438
valid_sources[0x3f]	17954	1			T1	26		T2	380		T30	3
valid_sources[0x40]	16013	1			T1	15		T2	419		T20	1
valid_sources[0x41]	14295	1			T5	2		T7	1		T4	1
valid_sources[0x42]	15730	1			T1	16		T2	325		T31	3
valid_sources[0x43]	15852	1			T6	1		T1	9		T18	5
valid_sources[0x44]	15436	1			T6	1		T1	14		T2	399
valid_sources[0x45]	15137	1			T4	2		T1	16		T2	401
valid_sources[0x46]	15620	1			T1	14		T17	1		T2	365
valid_sources[0x47]	15350	1			T1	8		T2	432		T30	1
valid_sources[0x48]	16522	1			T1	11		T18	7		T2	266
valid_sources[0x49]	16763	1			T1	11		T18	2		T2	458
valid_sources[0x4a]	17235	1			T25	2		T1	28		T2	335
valid_sources[0x4b]	14415	1			T1	10		T2	399		T31	5
valid_sources[0x4c]	15527	1			T1	18		T2	378		T31	6
valid_sources[0x4d]	16404	1			T5	1		T6	1		T26	1
valid_sources[0x4e]	16758	1			T1	5		T2	444		T30	2
valid_sources[0x4f]	15331	1			T1	17		T2	404		T30	4
valid_sources[0x50]	15479	1			T6	2		T1	12		T2	382
valid_sources[0x51]	15192	1			T6	1		T1	10		T2	347
valid_sources[0x52]	14767	1			T6	2		T1	13		T18	1
valid_sources[0x53]	17701	1			T1	4		T2	399		T30	2
valid_sources[0x54]	14661	1			T6	1		T25	1		T1	1
valid_sources[0x55]	14144	1			T4	2		T1	8		T2	404
valid_sources[0x56]	14999	1			T1	12		T2	316		T30	2
valid_sources[0x57]	16062	1			T1	13		T2	375		T31	5
valid_sources[0x58]	15638	1			T1	17		T2	383		T31	1
valid_sources[0x59]	14983	1			T4	1		T1	10		T2	342
valid_sources[0x5a]	15188	1			T1	9		T2	357		T31	1
valid_sources[0x5b]	15438	1			T7	18		T1	12		T2	360
valid_sources[0x5c]	16182	1			T6	1		T1	7		T2	337
valid_sources[0x5d]	16057	1			T1	10		T2	359		T31	4
valid_sources[0x5e]	16213	1			T1	13		T2	397		T31	3
valid_sources[0x5f]	14744	1			T4	2		T1	10		T2	367
valid_sources[0x60]	15977	1			T1	11		T2	336		T3	254
valid_sources[0x61]	14983	1			T1	8		T2	279		T31	4
valid_sources[0x62]	14563	1			T7	1		T24	1		T1	9
valid_sources[0x63]	14597	1			T1	10		T2	298		T71	4
valid_sources[0x64]	15580	1			T1	15		T2	450		T30	1
valid_sources[0x65]	16176	1			T7	6		T1	3		T2	387
valid_sources[0x66]	15294	1			T1	15		T2	436		T20	2
valid_sources[0x67]	14284	1			T1	7		T2	354		T21	3
valid_sources[0x68]	16954	1			T1	9		T17	1		T2	354
valid_sources[0x69]	15468	1			T24	1		T1	8		T18	1
valid_sources[0x6a]	15286	1			T6	1		T1	7		T2	358
valid_sources[0x6b]	15951	1			T1	13		T2	338		T71	1
valid_sources[0x6c]	14971	1			T1	6		T2	447		T30	1
valid_sources[0x6d]	13994	1			T6	1		T1	4		T2	394
valid_sources[0x6e]	16374	1			T6	3		T1	11		T2	369
valid_sources[0x6f]	15150	1			T7	1		T4	1		T1	12
valid_sources[0x70]	14350	1			T1	8		T18	2		T2	360
valid_sources[0x71]	15310	1			T6	1		T1	18		T2	313
valid_sources[0x72]	15963	1			T6	1		T1	7		T2	333
valid_sources[0x73]	15740	1			T1	20		T18	3		T2	352
valid_sources[0x74]	15068	1			T26	4		T1	14		T2	425
valid_sources[0x75]	14745	1			T1	13		T2	346		T31	3
valid_sources[0x76]	14261	1			T1	5		T2	397		T31	1
valid_sources[0x77]	16237	1			T1	1		T2	341		T72	1
valid_sources[0x78]	13963	1			T1	8		T17	1		T2	427
valid_sources[0x79]	14863	1			T1	18		T2	339		T31	3
valid_sources[0x7a]	13748	1			T4	1		T1	14		T2	419
valid_sources[0x7b]	14153	1			T1	11		T2	400		T20	3
valid_sources[0x7c]	14273	1			T6	1		T7	2		T26	6
valid_sources[0x7d]	15724	1			T6	1		T7	1		T1	3
valid_sources[0x7e]	16255	1			T1	8		T17	1		T2	440
valid_sources[0x7f]	14779	1			T1	6		T2	396		T30	3
valid_sources[0x80]	14850	1			T26	7		T1	5		T2	362

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

843493

1

T6

7

T7

13

T4

19

values[0x0]

all_enables

biggest_size

1273112

1

T5

4

T6

7

T7

6

values[0x1]

all_enables

biggest_size

1226295

1

T5

2

T6

4

T7

3