Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T26,T1
0	1	Covered	T1,T2,T21
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T26,T1
1	0	Covered	T16,T38,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1400601313	13227	0	0
GateOpen_A	1400601313	20260	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1400601313	13227	0	0
T1	1911114	54	0	0
T2	2169880	404	0	0
T3	0	107	0	0
T16	4571	11	0	0
T17	5562	0	0	0
T18	6048	4	0	0
T19	7191	0	0	0
T20	3424	0	0	0
T21	9969	17	0	0
T22	4574	0	0	0
T23	0	22	0	0
T26	4944	4	0	0
T71	0	34	0	0
T182	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1400601313	20260	0	0
T1	1911114	66	0	0
T2	0	430	0	0
T4	24404	12	0	0
T7	5304	4	0	0
T16	4571	15	0	0
T17	5562	0	0	0
T18	6048	8	0	0
T19	7191	4	0	0
T20	0	4	0	0
T24	23216	4	0	0
T25	4220	0	0	0
T26	4944	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T26,T1
0	1	Covered	T1,T2,T21
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T26,T1
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	154816890	3155	0	0
GateOpen_A	154816890	4911	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816890	3155	0	0
T1	208295	11	0	0
T2	399082	94	0	0
T3	0	28	0	0
T16	499	3	0	0
T17	631	0	0	0
T18	661	1	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1104	4	0	0
T22	524	0	0	0
T23	0	5	0	0
T26	541	1	0	0
T71	0	8	0	0
T182	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816890	4911	0	0
T1	208295	14	0	0
T2	0	100	0	0
T4	1506	3	0	0
T7	614	1	0	0
T16	499	4	0	0
T17	631	0	0	0
T18	661	2	0	0
T19	797	1	0	0
T20	0	1	0	0
T24	2668	1	0	0
T25	463	0	0	0
T26	541	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T26,T1
0	1	Covered	T1,T2,T21
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T26,T1
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	309634569	3357	0	0
GateOpen_A	309634569	5114	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309634569	3357	0	0
T1	416593	14	0	0
T2	798168	99	0	0
T3	0	26	0	0
T16	997	3	0	0
T17	1262	0	0	0
T18	1322	1	0	0
T19	1593	0	0	0
T20	716	0	0	0
T21	2207	5	0	0
T22	1049	0	0	0
T23	0	6	0	0
T26	1082	1	0	0
T71	0	9	0	0
T182	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309634569	5114	0	0
T1	416593	17	0	0
T2	0	105	0	0
T4	3011	3	0	0
T7	1229	1	0	0
T16	997	4	0	0
T17	1262	0	0	0
T18	1322	2	0	0
T19	1593	1	0	0
T20	0	1	0	0
T24	5336	1	0	0
T25	925	0	0	0
T26	1082	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T26,T1
0	1	Covered	T1,T2,T21
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T26,T1
1	0	Covered	T16,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	620579475	3366	0	0
GateOpen_A	620579475	5126	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620579475	3366	0	0
T1	832511	15	0	0
T2	159586	102	0	0
T3	0	24	0	0
T16	2017	3	0	0
T17	2446	0	0	0
T18	2710	1	0	0
T19	3200	0	0	0
T20	1567	0	0	0
T21	4438	4	0	0
T22	2001	0	0	0
T23	0	6	0	0
T26	2214	1	0	0
T71	0	9	0	0
T182	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620579475	5126	0	0
T1	832511	18	0	0
T2	0	109	0	0
T4	13258	3	0	0
T7	2307	1	0	0
T16	2017	4	0	0
T17	2446	0	0	0
T18	2710	2	0	0
T19	3200	1	0	0
T20	0	1	0	0
T24	10141	1	0	0
T25	1888	0	0	0
T26	2214	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T26,T1
0	1	Covered	T1,T2,T21
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T26,T1
1	0	Covered	T16,T38,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	315570379	3349	0	0
GateOpen_A	315570379	5109	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315570379	3349	0	0
T1	453715	14	0	0
T2	813044	109	0	0
T3	0	29	0	0
T16	1058	2	0	0
T17	1223	0	0	0
T18	1355	1	0	0
T19	1601	0	0	0
T20	783	0	0	0
T21	2220	4	0	0
T22	1000	0	0	0
T23	0	5	0	0
T26	1107	1	0	0
T71	0	8	0	0
T182	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315570379	5109	0	0
T1	453715	17	0	0
T2	0	116	0	0
T4	6629	3	0	0
T7	1154	1	0	0
T16	1058	3	0	0
T17	1223	0	0	0
T18	1355	2	0	0
T19	1601	1	0	0
T20	0	1	0	0
T24	5071	1	0	0
T25	944	0	0	0
T26	1107	2	0	0