Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	773811705	67062	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	773811705	67062	0	0
T1	2297380	722	0	0
T2	1801815	1194	0	0
T3	0	718	0	0
T9	0	90	0	0
T10	0	189	0	0
T11	0	266	0	0
T12	0	681	0	0
T13	0	316	0	0
T14	0	55	0	0
T15	0	196	0	0
T16	5720	0	0	0
T17	5860	0	0	0
T18	6915	0	0	0
T19	3500	0	0	0
T20	7915	0	0	0
T21	5775	0	0	0
T22	10420	0	0	0
T23	4180	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154762341	10119	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	10119	0	0
T1	459476	101	0	0
T2	360363	190	0	0
T3	0	129	0	0
T9	0	13	0	0
T10	0	30	0	0
T11	0	42	0	0
T12	0	90	0	0
T13	0	41	0	0
T14	0	9	0	0
T15	0	25	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154762341	10060	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	10060	0	0
T1	459476	101	0	0
T2	360363	191	0	0
T3	0	129	0	0
T9	0	11	0	0
T10	0	29	0	0
T11	0	42	0	0
T12	0	88	0	0
T13	0	45	0	0
T14	0	9	0	0
T15	0	25	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154762341	13459	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	13459	0	0
T1	459476	162	0	0
T2	360363	242	0	0
T3	0	140	0	0
T9	0	17	0	0
T10	0	38	0	0
T11	0	55	0	0
T12	0	138	0	0
T13	0	64	0	0
T14	0	11	0	0
T15	0	39	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154762341	13446	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	13446	0	0
T1	459476	140	0	0
T2	360363	243	0	0
T3	0	140	0	0
T9	0	18	0	0
T10	0	38	0	0
T11	0	53	0	0
T12	0	139	0	0
T13	0	62	0	0
T14	0	11	0	0
T15	0	41	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154762341	19978	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	19978	0	0
T1	459476	218	0	0
T2	360363	328	0	0
T3	0	180	0	0
T9	0	31	0	0
T10	0	54	0	0
T11	0	74	0	0
T12	0	226	0	0
T13	0	104	0	0
T14	0	15	0	0
T15	0	66	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0