Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	154762341	152731209	0	0
AllClkBypReqTrue_A	154762341	131925	0	0
IoClkBypReqFalse_A	154762341	152655226	0	2415
IoClkBypReqTrue_A	154762341	203028	0	0
LcClkBypAckFalse_A	154762341	152743213	0	0
LcClkBypAckTrue_A	154762341	119921	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	152731209	0	0
T1	459476	458261	0	0
T4	13120	1584	0	0
T5	1069	1036	0	0
T6	1941	1604	0	0
T7	2403	1779	0	0
T16	1144	1116	0	0
T17	1172	1075	0	0
T24	1055	1004	0	0
T25	1257	1194	0	0
T26	2238	2142	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	131925	0	0
T1	459476	491	0	0
T2	0	3335	0	0
T3	0	796	0	0
T4	13120	0	0	0
T6	1941	254	0	0
T7	2403	354	0	0
T16	1144	0	0	0
T17	1172	71	0	0
T18	1383	0	0	0
T19	0	6	0	0
T22	0	91	0	0
T24	1055	44	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T72	0	16	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	152655226	0	2415
T1	459476	457938	0	3
T4	13120	1578	0	3
T5	1069	1034	0	3
T6	1941	1601	0	3
T7	2403	1778	0	3
T16	1144	1114	0	3
T17	1172	1144	0	3
T24	1055	963	0	3
T25	1257	1192	0	3
T26	2238	2140	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	203028	0	0
T1	459476	794	0	0
T2	0	5080	0	0
T3	0	1402	0	0
T4	13120	0	0	0
T6	1941	255	0	0
T7	2403	353	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T22	0	196	0	0
T24	1055	83	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T72	0	34	0	0
T113	0	89	0	0
T114	0	466	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	152743213	0	0
T1	459476	458182	0	0
T4	13120	1584	0	0
T5	1069	1036	0	0
T6	1941	1735	0	0
T7	2403	1905	0	0
T16	1144	1116	0	0
T17	1172	1146	0	0
T24	1055	1029	0	0
T25	1257	1194	0	0
T26	2238	2142	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	119921	0	0
T1	459476	570	0	0
T2	0	3132	0	0
T3	0	769	0	0
T4	13120	0	0	0
T6	1941	123	0	0
T7	2403	228	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T22	0	173	0	0
T24	1055	19	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T72	0	29	0	0
T113	0	50	0	0
T114	0	386	0	0