Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15881	0	0
TransStop_A	2147483647	8181	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15881	0	0
T1	3612904	118	0	0
T2	679684	414	0	0
T3	0	163	0	0
T10	0	20	0	0
T16	8464	0	0	0
T17	10192	0	0	0
T18	11292	4	0	0
T19	13332	0	0	0
T20	6528	5	0	0
T21	18496	0	0	0
T22	8340	0	0	0
T26	9228	4	0	0
T85	0	3	0	0
T115	0	33	0	0
T116	0	14	0	0
T117	0	14	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8181	0	0
T1	3612904	49	0	0
T2	679684	234	0	0
T3	0	81	0	0
T10	0	10	0	0
T16	8464	0	0	0
T17	10192	0	0	0
T18	11292	4	0	0
T19	13332	0	0	0
T20	6528	3	0	0
T21	18496	0	0	0
T22	8340	0	0	0
T26	9228	4	0	0
T85	0	1	0	0
T115	0	14	0	0
T116	0	7	0	0
T117	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	657506907	3939	0	0
TransStop_A	657506907	2074	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	3939	0	0
T1	903226	30	0	0
T2	169921	105	0	0
T3	0	45	0	0
T10	0	4	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	0	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T85	0	3	0	0
T115	0	7	0	0
T116	0	5	0	0
T117	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	2074	0	0
T1	903226	13	0	0
T2	169921	58	0	0
T3	0	22	0	0
T10	0	2	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	0	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T85	0	1	0	0
T115	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	657506907	3971	0	0
TransStop_A	657506907	2061	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	3971	0	0
T1	903226	27	0	0
T2	169921	106	0	0
T3	0	38	0	0
T10	0	6	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	1	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T115	0	10	0	0
T116	0	4	0	0
T117	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	2061	0	0
T1	903226	11	0	0
T2	169921	60	0	0
T3	0	19	0	0
T10	0	4	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	1	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T115	0	4	0	0
T116	0	2	0	0
T117	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	657506907	3919	0	0
TransStop_A	657506907	1964	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	3919	0	0
T1	903226	30	0	0
T2	169921	99	0	0
T3	0	38	0	0
T10	0	4	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	2	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T115	0	7	0	0
T116	0	3	0	0
T117	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	1964	0	0
T1	903226	12	0	0
T2	169921	59	0	0
T3	0	16	0	0
T10	0	1	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	1	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T115	0	3	0	0
T116	0	1	0	0
T117	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	657506907	4052	0	0
TransStop_A	657506907	2082	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	4052	0	0
T1	903226	31	0	0
T2	169921	104	0	0
T3	0	42	0	0
T10	0	6	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	2	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T115	0	9	0	0
T116	0	2	0	0
T117	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506907	2082	0	0
T1	903226	13	0	0
T2	169921	57	0	0
T3	0	24	0	0
T10	0	3	0	0
T16	2116	0	0	0
T17	2548	0	0	0
T18	2823	1	0	0
T19	3333	0	0	0
T20	1632	1	0	0
T21	4624	0	0	0
T22	2085	0	0	0
T26	2307	1	0	0
T115	0	4	0	0
T116	0	2	0	0
T117	0	3	0	0