Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	154762341	20337472	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	20337472	0	57
T1	459476	65448	0	0
T2	360363	177449	0	0
T3	0	251985	0	0
T9	0	12613	0	1
T10	0	12447	0	0
T11	0	17378	0	1
T12	0	83285	0	0
T13	0	37310	0	1
T14	0	3942	0	1
T15	0	0	0	1
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T27	0	808	0	1
T28	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1
T120	0	0	0	1