Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	155687523	4858382	0	0
clk_enables_rd_A	155687523	57576	0	0
clk_hints_rd_A	155687523	50228	0	0
extclk_ctrl_rd_A	155687523	64461	0	0
extclk_ctrl_regwen_rd_A	155687523	48334	0	0
jitter_enable_rd_A	155687523	69694	0	0
jitter_regwen_rd_A	155687523	55579	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	4858382	0	0
T2	360363	119925	0	0
T3	0	37239	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T31	33532	0	0	0
T34	1598	0	0	0
T41	0	44743	0	0
T64	0	90658	0	0
T65	0	100705	0	0
T66	0	113593	0	0
T67	0	83785	0	0
T68	0	34275	0	0
T69	0	88404	0	0
T70	0	87212	0	0
T71	1094	0	0	0
T72	1648	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	57576	0	0
T29	196290	0	0	0
T41	0	1769	0	0
T67	0	3373	0	0
T70	0	3586	0	0
T98	9599	0	0	0
T138	2584	3	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	8	0	0
T142	0	2	0	0
T143	0	5067	0	0
T144	0	1520	0	0
T145	2592	0	0	0
T146	30680	0	0	0
T147	1765	0	0	0
T148	1134	0	0	0
T149	2274	0	0	0
T150	2529	0	0	0
T151	1486	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	50228	0	0
T1	459476	0	0	0
T2	360363	0	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T26	2238	2	0	0
T41	0	1613	0	0
T67	0	2875	0	0
T70	0	2920	0	0
T138	0	4	0	0
T139	0	5	0	0
T140	0	7	0	0
T141	0	6	0	0
T142	0	7	0	0
T152	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	64461	0	0
T1	459476	0	0	0
T4	13120	0	0	0
T7	2403	53	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	11	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T46	0	28	0	0
T47	0	9	0	0
T73	0	33	0	0
T153	0	9	0	0
T154	0	64	0	0
T155	0	39	0	0
T156	0	17	0	0
T157	0	14	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	48334	0	0
T29	196290	0	0	0
T41	0	1579	0	0
T67	0	2782	0	0
T70	0	3099	0	0
T98	9599	14	0	0
T110	0	33	0	0
T143	0	4551	0	0
T144	0	1273	0	0
T146	30680	0	0	0
T147	1765	0	0	0
T148	1134	0	0	0
T149	2274	0	0	0
T150	2529	0	0	0
T151	1486	0	0	0
T158	0	10	0	0
T159	0	4574	0	0
T160	0	26	0	0
T161	692	0	0	0
T162	2129	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	69694	0	0
T1	459476	0	0	0
T2	360363	0	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T26	2238	60	0	0
T41	0	1986	0	0
T67	0	4012	0	0
T138	0	116	0	0
T139	0	437	0	0
T140	0	94	0	0
T141	0	107	0	0
T152	0	73	0	0
T163	0	61	0	0
T164	0	73	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	55579	0	0
T41	146725	1597	0	0
T64	188917	0	0	0
T67	0	3288	0	0
T70	0	3526	0	0
T88	1753	0	0	0
T143	0	5087	0	0
T144	0	1705	0	0
T159	0	5703	0	0
T165	0	5052	0	0
T166	0	5461	0	0
T167	0	3062	0	0
T168	0	2311	0	0
T169	1036	0	0	0
T170	113780	0	0	0
T171	668	0	0	0
T172	30890	0	0	0
T173	905	0	0	0
T174	1100	0	0	0
T175	2113	0	0	0