Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T31
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1556875230	1316387	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1556875230	278709	0	0
SrcBusyKnown_A	1556875230	1536912540	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556875230	1316387	0	0
T1	4594760	8139	0	0
T2	3603630	27123	0	0
T3	0	6828	0	0
T4	131200	466	0	0
T9	0	848	0	0
T10	0	1868	0	0
T16	11440	0	0	0
T17	11720	0	0	0
T18	13830	0	0	0
T19	7000	0	0	0
T24	10550	0	0	0
T25	12570	0	0	0
T26	22380	0	0	0
T30	0	356	0	0
T31	0	1892	0	0
T32	0	2473	0	0
T33	0	698	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5628676	5620242	0	0
T4	76422	10554	0	0
T5	32120	31200	0	0
T6	25570	24602	0	0
T7	15410	13912	0	0
T16	13368	13060	0	0
T17	16220	15912	0	0
T24	67552	67154	0	0
T25	12366	11806	0	0
T26	14498	13962	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556875230	278709	0	0
T1	4594760	1540	0	0
T2	3603630	8195	0	0
T3	0	2420	0	0
T4	131200	56	0	0
T9	0	100	0	0
T10	0	540	0	0
T16	11440	0	0	0
T17	11720	0	0	0
T18	13830	0	0	0
T19	7000	0	0	0
T24	10550	0	0	0
T25	12570	0	0	0
T26	22380	0	0	0
T30	0	100	0	0
T31	0	548	0	0
T32	0	300	0	0
T33	0	240	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556875230	1536912540	0	0
T1	4594760	4587620	0	0
T4	131200	15870	0	0
T5	10690	10370	0	0
T6	19410	18590	0	0
T7	24030	21340	0	0
T16	11440	11170	0	0
T17	11720	11470	0	0
T24	10550	10490	0	0
T25	12570	11950	0	0
T26	22380	21430	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	83913	0	0
DstReqKnown_A	623446524	619242118	0	0
SrcAckBusyChk_A	155687523	25137	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	83913	0	0
T1	459476	547	0	0
T2	360363	2060	0	0
T3	0	604	0	0
T4	13120	22	0	0
T9	0	60	0	0
T10	0	137	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	26	0	0
T31	0	98	0	0
T32	0	154	0	0
T33	0	60	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623446524	619242118	0	0
T1	832510	831075	0	0
T4	13258	1603	0	0
T5	4887	4739	0	0
T6	3803	3641	0	0
T7	2307	2049	0	0
T16	2017	1965	0	0
T17	2446	2394	0	0
T24	10141	10075	0	0
T25	1887	1793	0	0
T26	2214	2121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	25137	0	0
T1	459476	154	0	0
T2	360363	814	0	0
T3	0	240	0	0
T4	13120	4	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	38	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	117791	0	0
DstReqKnown_A	311020613	309978232	0	0
SrcAckBusyChk_A	155687523	25137	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	117791	0	0
T1	459476	786	0	0
T2	360363	2757	0	0
T3	0	641	0	0
T4	13120	33	0	0
T9	0	84	0	0
T10	0	195	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	37	0	0
T31	0	136	0	0
T32	0	249	0	0
T33	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311020613	309978232	0	0
T1	416593	416213	0	0
T4	3010	802	0	0
T5	2425	2370	0	0
T6	2082	2034	0	0
T7	1228	1166	0	0
T16	996	982	0	0
T17	1262	1248	0	0
T24	5335	5314	0	0
T25	924	896	0	0
T26	1081	1060	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	25137	0	0
T1	459476	154	0	0
T2	360363	814	0	0
T3	0	240	0	0
T4	13120	4	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	38	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	184652	0	0
DstReqKnown_A	155509710	154988673	0	0
SrcAckBusyChk_A	155687523	25137	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	184652	0	0
T1	459476	1259	0	0
T2	360363	3837	0	0
T3	0	879	0	0
T4	13120	61	0	0
T9	0	150	0	0
T10	0	279	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	52	0	0
T31	0	196	0	0
T32	0	437	0	0
T33	0	93	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155509710	154988673	0	0
T1	208294	208104	0	0
T4	1505	401	0	0
T5	1212	1184	0	0
T6	1038	1014	0	0
T7	614	583	0	0
T16	498	491	0	0
T17	631	624	0	0
T24	2667	2657	0	0
T25	462	448	0	0
T26	541	531	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	25137	0	0
T1	459476	154	0	0
T2	360363	814	0	0
T3	0	240	0	0
T4	13120	4	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	38	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	83919	0	0
DstReqKnown_A	660493549	656054951	0	0
SrcAckBusyChk_A	155687523	25137	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	83919	0	0
T1	459476	544	0	0
T2	360363	2060	0	0
T3	0	604	0	0
T4	13120	22	0	0
T9	0	50	0	0
T10	0	134	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	26	0	0
T31	0	98	0	0
T32	0	152	0	0
T33	0	60	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660493549	656054951	0	0
T1	903226	901728	0	0
T4	13810	1670	0	0
T5	5092	4937	0	0
T6	3961	3792	0	0
T7	2403	2134	0	0
T16	2116	2061	0	0
T17	2548	2493	0	0
T24	10563	10494	0	0
T25	1966	1869	0	0
T26	2307	2209	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	25137	0	0
T1	459476	154	0	0
T2	360363	814	0	0
T3	0	240	0	0
T4	13120	4	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	38	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	116433	0	0
DstReqKnown_A	317003723	314886149	0	0
SrcAckBusyChk_A	155687523	24681	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	116433	0	0
T1	459476	940	0	0
T2	360363	2776	0	0
T3	0	640	0	0
T4	13120	18	0	0
T9	0	82	0	0
T10	0	191	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	36	0	0
T31	0	85	0	0
T32	0	251	0	0
T33	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317003723	314886149	0	0
T1	453715	453001	0	0
T4	6628	801	0	0
T5	2444	2370	0	0
T6	1901	1820	0	0
T7	1153	1024	0	0
T16	1057	1031	0	0
T17	1223	1197	0	0
T24	5070	5037	0	0
T25	944	897	0	0
T26	1106	1060	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	24681	0	0
T1	459476	154	0	0
T2	360363	814	0	0
T3	0	240	0	0
T4	13120	2	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	19	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T31
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	104208	0	0
DstReqKnown_A	623446524	619242118	0	0
SrcAckBusyChk_A	155687523	30834	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	104208	0	0
T1	459476	547	0	0
T2	360363	2083	0	0
T3	0	618	0	0
T4	13120	40	0	0
T9	0	60	0	0
T10	0	139	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	26	0	0
T31	0	188	0	0
T32	0	156	0	0
T33	0	60	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	623446524	619242118	0	0
T1	832510	831075	0	0
T4	13258	1603	0	0
T5	4887	4739	0	0
T6	3803	3641	0	0
T7	2307	2049	0	0
T16	2017	1965	0	0
T17	2446	2394	0	0
T24	10141	10075	0	0
T25	1887	1793	0	0
T26	2214	2121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	30834	0	0
T1	459476	154	0	0
T2	360363	825	0	0
T3	0	244	0	0
T4	13120	8	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	76	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T31
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	146033	0	0
DstReqKnown_A	311020613	309978232	0	0
SrcAckBusyChk_A	155687523	30741	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	146033	0	0
T1	459476	786	0	0
T2	360363	2799	0	0
T3	0	659	0	0
T4	13120	62	0	0
T9	0	86	0	0
T10	0	191	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	36	0	0
T31	0	264	0	0
T32	0	247	0	0
T33	0	70	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311020613	309978232	0	0
T1	416593	416213	0	0
T4	3010	802	0	0
T5	2425	2370	0	0
T6	2082	2034	0	0
T7	1228	1166	0	0
T16	996	982	0	0
T17	1262	1248	0	0
T24	5335	5314	0	0
T25	924	896	0	0
T26	1081	1060	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	30741	0	0
T1	459476	154	0	0
T2	360363	825	0	0
T3	0	244	0	0
T4	13120	8	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	76	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T31
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	230465	0	0
DstReqKnown_A	155509710	154988673	0	0
SrcAckBusyChk_A	155687523	30756	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	230465	0	0
T1	459476	1246	0	0
T2	360363	3864	0	0
T3	0	901	0	0
T4	13120	113	0	0
T9	0	149	0	0
T10	0	278	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	54	0	0
T31	0	376	0	0
T32	0	427	0	0
T33	0	94	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155509710	154988673	0	0
T1	208294	208104	0	0
T4	1505	401	0	0
T5	1212	1184	0	0
T6	1038	1014	0	0
T7	614	583	0	0
T16	498	491	0	0
T17	631	624	0	0
T24	2667	2657	0	0
T25	462	448	0	0
T26	541	531	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	30756	0	0
T1	459476	154	0	0
T2	360363	825	0	0
T3	0	244	0	0
T4	13120	8	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	76	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T31
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	103411	0	0
DstReqKnown_A	660493549	656054951	0	0
SrcAckBusyChk_A	155687523	30732	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	103411	0	0
T1	459476	544	0	0
T2	360363	2083	0	0
T3	0	618	0	0
T4	13120	39	0	0
T9	0	49	0	0
T10	0	134	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	26	0	0
T31	0	188	0	0
T32	0	152	0	0
T33	0	60	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660493549	656054951	0	0
T1	903226	901728	0	0
T4	13810	1670	0	0
T5	5092	4937	0	0
T6	3961	3792	0	0
T7	2403	2134	0	0
T16	2116	2061	0	0
T17	2548	2493	0	0
T24	10563	10494	0	0
T25	1966	1869	0	0
T26	2307	2209	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	30732	0	0
T1	459476	154	0	0
T2	360363	825	0	0
T3	0	244	0	0
T4	13120	8	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	76	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T31
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	155687523	145562	0	0
DstReqKnown_A	317003723	314886149	0	0
SrcAckBusyChk_A	155687523	30417	0	0
SrcBusyKnown_A	155687523	153691254	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	145562	0	0
T1	459476	940	0	0
T2	360363	2804	0	0
T3	0	664	0	0
T4	13120	56	0	0
T9	0	78	0	0
T10	0	190	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	37	0	0
T31	0	263	0	0
T32	0	248	0	0
T33	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	317003723	314886149	0	0
T1	453715	453001	0	0
T4	6628	801	0	0
T5	2444	2370	0	0
T6	1901	1820	0	0
T7	1153	1024	0	0
T16	1057	1031	0	0
T17	1223	1197	0	0
T24	5070	5037	0	0
T25	944	897	0	0
T26	1106	1060	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	30417	0	0
T1	459476	154	0	0
T2	360363	825	0	0
T3	0	244	0	0
T4	13120	6	0	0
T9	0	10	0	0
T10	0	54	0	0
T16	1144	0	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T24	1055	0	0	0
T25	1257	0	0	0
T26	2238	0	0	0
T30	0	10	0	0
T31	0	73	0	0
T32	0	30	0	0
T33	0	24	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155687523	153691254	0	0
T1	459476	458762	0	0
T4	13120	1587	0	0
T5	1069	1037	0	0
T6	1941	1859	0	0
T7	2403	2134	0	0
T16	1144	1117	0	0
T17	1172	1147	0	0
T24	1055	1049	0	0
T25	1257	1195	0	0
T26	2238	2143	0	0