Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	464287023	412	0	0
StatusRise_A	464287023	412	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464287023	412	0	0
T2	1081089	0	0	0
T16	3432	7	0	0
T17	3516	0	0	0
T18	4149	0	0	0
T19	2100	0	0	0
T20	4749	0	0	0
T21	3465	0	0	0
T22	6252	0	0	0
T23	2508	0	0	0
T30	48144	0	0	0
T38	0	10	0	0
T39	0	8	0	0
T40	0	3	0	0
T148	0	9	0	0
T171	0	2	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	6	0	0
T179	0	9	0	0
T180	0	9	0	0
T181	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464287023	412	0	0
T2	1081089	0	0	0
T16	3432	7	0	0
T17	3516	0	0	0
T18	4149	0	0	0
T19	2100	0	0	0
T20	4749	0	0	0
T21	3465	0	0	0
T22	6252	0	0	0
T23	2508	0	0	0
T30	48144	0	0	0
T38	0	10	0	0
T39	0	8	0	0
T40	0	3	0	0
T148	0	9	0	0
T171	0	2	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	6	0	0
T179	0	9	0	0
T180	0	9	0	0
T181	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154762341	147	0	0
StatusRise_A	154762341	147	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	147	0	0
T2	360363	0	0	0
T16	1144	2	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	147	0	0
T2	360363	0	0	0
T16	1144	2	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154762341	131	0	0
StatusRise_A	154762341	131	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	131	0	0
T2	360363	0	0	0
T16	1144	3	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	5	0	0
T181	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	131	0	0
T2	360363	0	0	0
T16	1144	3	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	5	0	0
T181	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154762341	134	0	0
StatusRise_A	154762341	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	134	0	0
T2	360363	0	0	0
T16	1144	2	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T40	0	1	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T178	0	2	0	0
T179	0	3	0	0
T180	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154762341	134	0	0
T2	360363	0	0	0
T16	1144	2	0	0
T17	1172	0	0	0
T18	1383	0	0	0
T19	700	0	0	0
T20	1583	0	0	0
T21	1155	0	0	0
T22	2084	0	0	0
T23	836	0	0	0
T30	16048	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T40	0	1	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T178	0	2	0	0
T179	0	3	0	0
T180	0	4	0	0