Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47879	0	0
CgEnOn_A	2147483647	38101	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47879	0	0
T1	5524016	137	0	0
T2	3987570	110	0	0
T3	0	50	0	0
T4	24401	9	0	0
T5	10968	3	0	0
T6	8824	3	0	0
T7	5302	3	0	0
T16	22828	29	0	0
T17	27674	3	0	0
T18	24301	1	0	0
T19	28782	0	0	0
T20	13925	0	0	0
T21	39911	0	0	0
T22	18123	0	0	0
T23	32272	0	0	0
T24	23213	3	0	0
T25	4217	3	0	0
T26	14170	7	0	0
T30	269965	0	0	0
T38	0	19	0	0
T39	0	10	0	0
T65	0	5	0	0
T115	0	7	0	0
T148	0	15	0	0
T176	0	5	0	0
T177	0	5	0	0
T178	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38101	0	0
T1	5524016	107	0	0
T2	6157450	558	0	0
T3	0	198	0	0
T16	22828	26	0	0
T17	27674	0	0	0
T18	30348	4	0	0
T19	35972	0	0	0
T20	17348	0	0	0
T21	49878	24	0	0
T22	22696	0	0	0
T23	32272	31	0	0
T26	14170	4	0	0
T30	269965	0	0	0
T38	0	19	0	0
T39	0	10	0	0
T71	0	30	0	0
T115	0	7	0	0
T116	0	5	0	0
T148	0	15	0	0
T176	0	5	0	0
T177	0	5	0	0
T178	0	15	0	0
T179	0	15	0	0
T180	0	5	0	0
T181	0	3	0	0
T182	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	309634173	139	0	0
CgEnOn_A	309634173	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309634173	139	0	0
T2	798168	1	0	0
T3	0	1	0	0
T16	996	3	0	0
T17	1262	0	0	0
T18	1322	0	0	0
T19	1593	0	0	0
T20	716	0	0	0
T21	2207	0	0	0
T22	1049	0	0	0
T23	3319	0	0	0
T30	27907	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T65	0	1	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309634173	138	0	0
T2	798168	1	0	0
T3	0	1	0	0
T16	996	3	0	0
T17	1262	0	0	0
T18	1322	0	0	0
T19	1593	0	0	0
T20	716	0	0	0
T21	2207	0	0	0
T22	1049	0	0	0
T23	3319	0	0	0
T30	27907	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	154816504	139	0	0
CgEnOn_A	154816504	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	139	0	0
T2	399082	1	0	0
T3	0	1	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	0	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	0	0	0
T22	523	0	0	0
T23	1660	0	0	0
T30	13954	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T65	0	1	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	138	0	0
T2	399082	1	0	0
T3	0	1	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	0	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	0	0	0
T22	523	0	0	0
T23	1660	0	0	0
T30	13954	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	154816504	139	0	0
CgEnOn_A	154816504	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	139	0	0
T2	399082	1	0	0
T3	0	1	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	0	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	0	0	0
T22	523	0	0	0
T23	1660	0	0	0
T30	13954	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T65	0	1	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	138	0	0
T2	399082	1	0	0
T3	0	1	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	0	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	0	0	0
T22	523	0	0	0
T23	1660	0	0	0
T30	13954	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	154816504	139	0	0
CgEnOn_A	154816504	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	139	0	0
T2	399082	1	0	0
T3	0	1	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	0	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	0	0	0
T22	523	0	0	0
T23	1660	0	0	0
T30	13954	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T65	0	1	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	138	0	0
T2	399082	1	0	0
T3	0	1	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	0	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	0	0	0
T22	523	0	0	0
T23	1660	0	0	0
T30	13954	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	620579046	139	0	0
CgEnOn_A	620579046	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620579046	139	0	0
T2	159586	1	0	0
T3	0	1	0	0
T16	2017	3	0	0
T17	2446	0	0	0
T18	2709	0	0	0
T19	3200	0	0	0
T20	1566	0	0	0
T21	4438	0	0	0
T22	2001	0	0	0
T23	6690	0	0	0
T30	55867	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T65	0	1	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620579046	131	0	0
T2	159586	0	0	0
T16	2017	3	0	0
T17	2446	0	0	0
T18	2709	0	0	0
T19	3200	0	0	0
T20	1566	0	0	0
T21	4438	0	0	0
T22	2001	0	0	0
T23	6690	0	0	0
T30	55867	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T148	0	3	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	5	0	0
T181	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	657506476	150	0	0
CgEnOn_A	657506476	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	150	0	0
T2	169921	0	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	0	0	0
T19	3333	0	0	0
T20	1631	0	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T23	6969	0	0	0
T30	58197	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T143	0	1	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	147	0	0
T2	169921	0	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	0	0	0
T19	3333	0	0	0
T20	1631	0	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T23	6969	0	0	0
T30	58197	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	657506476	150	0	0
CgEnOn_A	657506476	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	150	0	0
T2	169921	0	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	0	0	0
T19	3333	0	0	0
T20	1631	0	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T23	6969	0	0	0
T30	58197	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T143	0	1	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	147	0	0
T2	169921	0	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	0	0	0
T19	3333	0	0	0
T20	1631	0	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T23	6969	0	0	0
T30	58197	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	315569959	136	0	0
CgEnOn_A	315569959	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569959	136	0	0
T2	813044	0	0	0
T16	1057	2	0	0
T17	1223	0	0	0
T18	1355	0	0	0
T19	1600	0	0	0
T20	783	0	0	0
T21	2219	0	0	0
T22	1000	0	0	0
T23	3345	0	0	0
T30	27935	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T40	0	1	0	0
T70	0	1	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T178	0	2	0	0
T179	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569959	134	0	0
T2	813044	0	0	0
T16	1057	2	0	0
T17	1223	0	0	0
T18	1355	0	0	0
T19	1600	0	0	0
T20	783	0	0	0
T21	2219	0	0	0
T22	1000	0	0	0
T23	3345	0	0	0
T30	27935	0	0	0
T38	0	3	0	0
T39	0	2	0	0
T40	0	1	0	0
T148	0	3	0	0
T171	0	1	0	0
T176	0	2	0	0
T178	0	2	0	0
T179	0	3	0	0
T180	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	154816504	7540	0	0
CgEnOn_A	154816504	5107	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	7540	0	0
T1	208294	35	0	0
T4	1505	3	0	0
T5	1212	1	0	0
T6	1038	1	0	0
T7	614	1	0	0
T16	498	4	0	0
T17	631	1	0	0
T24	2667	1	0	0
T25	462	1	0	0
T26	541	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154816504	5107	0	0
T1	208294	25	0	0
T2	399082	148	0	0
T3	0	48	0	0
T16	498	3	0	0
T17	631	0	0	0
T18	661	1	0	0
T19	797	0	0	0
T20	358	0	0	0
T21	1103	9	0	0
T22	523	0	0	0
T23	0	10	0	0
T26	541	1	0	0
T71	0	11	0	0
T182	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	309634173	7573	0	0
CgEnOn_A	309634173	5140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309634173	7573	0	0
T1	416593	35	0	0
T4	3010	3	0	0
T5	2425	1	0	0
T6	2082	1	0	0
T7	1228	1	0	0
T16	996	4	0	0
T17	1262	1	0	0
T24	5335	1	0	0
T25	924	1	0	0
T26	1081	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	309634173	5140	0	0
T1	416593	25	0	0
T2	798168	150	0	0
T3	0	52	0	0
T16	996	3	0	0
T17	1262	0	0	0
T18	1322	1	0	0
T19	1593	0	0	0
T20	716	0	0	0
T21	2207	8	0	0
T22	1049	0	0	0
T23	0	10	0	0
T26	1081	1	0	0
T71	0	10	0	0
T182	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	620579046	7585	0	0
CgEnOn_A	620579046	5145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620579046	7585	0	0
T1	832510	37	0	0
T4	13258	3	0	0
T5	4887	1	0	0
T6	3803	1	0	0
T7	2307	1	0	0
T16	2017	4	0	0
T17	2446	1	0	0
T24	10141	1	0	0
T25	1887	1	0	0
T26	2214	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	620579046	5145	0	0
T1	832510	27	0	0
T2	159586	151	0	0
T3	0	49	0	0
T16	2017	3	0	0
T17	2446	0	0	0
T18	2709	1	0	0
T19	3200	0	0	0
T20	1566	0	0	0
T21	4438	7	0	0
T22	2001	0	0	0
T23	0	11	0	0
T26	2214	1	0	0
T71	0	9	0	0
T182	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	315569959	7569	0	0
CgEnOn_A	315569959	5129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569959	7569	0	0
T1	453715	37	0	0
T4	6628	3	0	0
T5	2444	1	0	0
T6	1901	1	0	0
T7	1153	1	0	0
T16	1057	3	0	0
T17	1223	1	0	0
T24	5070	1	0	0
T25	944	1	0	0
T26	1106	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315569959	5129	0	0
T1	453715	27	0	0
T2	813044	151	0	0
T3	0	51	0	0
T16	1057	2	0	0
T17	1223	0	0	0
T18	1355	1	0	0
T19	1600	0	0	0
T20	783	0	0	0
T21	2219	8	0	0
T22	1000	0	0	0
T23	0	9	0	0
T26	1106	1	0	0
T71	0	10	0	0
T182	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T26,T1,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	657506476	4089	0	0
CgEnOn_A	657506476	4086	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4089	0	0
T1	903226	30	0	0
T2	169921	105	0	0
T3	0	45	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	0	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T38	0	4	0	0
T115	0	7	0	0
T116	0	5	0	0
T117	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4086	0	0
T1	903226	30	0	0
T2	169921	105	0	0
T3	0	45	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	0	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T38	0	4	0	0
T115	0	7	0	0
T116	0	5	0	0
T117	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T26,T1,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	657506476	4121	0	0
CgEnOn_A	657506476	4118	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4121	0	0
T1	903226	27	0	0
T2	169921	106	0	0
T3	0	38	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	1	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T115	0	10	0	0
T116	0	4	0	0
T117	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4118	0	0
T1	903226	27	0	0
T2	169921	106	0	0
T3	0	38	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	1	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T115	0	10	0	0
T116	0	4	0	0
T117	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T26,T1,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	657506476	4069	0	0
CgEnOn_A	657506476	4066	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4069	0	0
T1	903226	30	0	0
T2	169921	99	0	0
T3	0	38	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	2	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T115	0	7	0	0
T116	0	3	0	0
T117	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4066	0	0
T1	903226	30	0	0
T2	169921	99	0	0
T3	0	38	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	2	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T115	0	7	0	0
T116	0	3	0	0
T117	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T26,T1,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	657506476	4202	0	0
CgEnOn_A	657506476	4199	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4202	0	0
T1	903226	31	0	0
T2	169921	104	0	0
T3	0	42	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	2	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T115	0	9	0	0
T116	0	2	0	0
T117	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	657506476	4199	0	0
T1	903226	31	0	0
T2	169921	104	0	0
T3	0	42	0	0
T16	2116	2	0	0
T17	2548	0	0	0
T18	2822	1	0	0
T19	3333	0	0	0
T20	1631	2	0	0
T21	4623	0	0	0
T22	2084	0	0	0
T26	2307	1	0	0
T115	0	9	0	0
T116	0	2	0	0
T117	0	4	0	0