Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3815020

1

T6

7

T7

13

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1095171	1			T6	10		T7	14		T8	2
values[0x0]	1548617	1			T6	11		T7	11		T8	1
values[0x1]	1822957	1			T6	10		T7	18		T8	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	356644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4110101

1

T6

8

T7

17

T8

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17588	1			T8	1		T1	3		T20	1
valid_sources[0x01]	17862	1			T1	1		T5	2		T2	239
valid_sources[0x02]	17555	1			T24	1		T25	3		T4	2
valid_sources[0x03]	16193	1			T1	1		T5	1		T2	228
valid_sources[0x04]	18028	1			T4	1		T2	259		T69	1
valid_sources[0x05]	16659	1			T4	4		T2	205		T3	14
valid_sources[0x06]	17300	1			T5	2		T2	248		T3	12
valid_sources[0x07]	17341	1			T4	2		T1	2		T2	256
valid_sources[0x08]	16711	1			T4	4		T5	1		T2	233
valid_sources[0x09]	17609	1			T4	2		T1	2		T5	1
valid_sources[0x0a]	17940	1			T4	14		T20	1		T5	2
valid_sources[0x0b]	16760	1			T4	2		T5	2		T2	246
valid_sources[0x0c]	17796	1			T4	1		T2	225		T37	1
valid_sources[0x0d]	16372	1			T1	2		T5	4		T2	255
valid_sources[0x0e]	16743	1			T4	1		T2	230		T69	1
valid_sources[0x0f]	16972	1			T4	3		T1	3		T17	1
valid_sources[0x10]	18346	1			T4	1		T17	1		T5	1
valid_sources[0x11]	17688	1			T4	1		T5	1		T2	232
valid_sources[0x12]	17954	1			T4	1		T5	1		T2	215
valid_sources[0x13]	17431	1			T7	1		T24	1		T4	2
valid_sources[0x14]	18305	1			T4	2		T1	1		T5	1
valid_sources[0x15]	17510	1			T7	6		T4	1		T1	1
valid_sources[0x16]	17469	1			T25	4		T4	2		T1	3
valid_sources[0x17]	17680	1			T4	4		T1	1		T17	1
valid_sources[0x18]	18434	1			T7	10		T4	5		T1	1
valid_sources[0x19]	18106	1			T4	1		T1	1		T5	2
valid_sources[0x1a]	16540	1			T1	2		T2	227		T3	8
valid_sources[0x1b]	17321	1			T4	3		T1	3		T5	1
valid_sources[0x1c]	17643	1			T4	1		T1	1		T2	257
valid_sources[0x1d]	17551	1			T5	2		T2	258		T70	2
valid_sources[0x1e]	17981	1			T4	1		T1	2		T2	230
valid_sources[0x1f]	18451	1			T4	3		T1	1		T17	1
valid_sources[0x20]	18916	1			T25	2		T5	1		T2	226
valid_sources[0x21]	18577	1			T25	11		T4	2		T1	1
valid_sources[0x22]	16137	1			T1	1		T5	2		T2	262
valid_sources[0x23]	20700	1			T1	3		T2	225		T66	3
valid_sources[0x24]	17346	1			T24	1		T4	2		T17	1
valid_sources[0x25]	17879	1			T24	1		T25	1		T4	1
valid_sources[0x26]	17841	1			T4	4		T1	2		T2	239
valid_sources[0x27]	16747	1			T4	4		T5	1		T2	222
valid_sources[0x28]	17871	1			T1	1		T5	1		T2	244
valid_sources[0x29]	16550	1			T4	2		T2	223		T3	6
valid_sources[0x2a]	17476	1			T1	2		T5	1		T2	246
valid_sources[0x2b]	16665	1			T1	1		T18	12		T5	2
valid_sources[0x2c]	20161	1			T4	2		T2	237		T32	1
valid_sources[0x2d]	17250	1			T1	1		T20	1		T5	3
valid_sources[0x2e]	18250	1			T4	2		T17	1		T2	275
valid_sources[0x2f]	17524	1			T25	4		T4	2		T1	1
valid_sources[0x30]	15199	1			T1	2		T2	225		T3	11
valid_sources[0x31]	17531	1			T4	1		T1	1		T2	254
valid_sources[0x32]	16052	1			T4	1		T1	1		T2	249
valid_sources[0x33]	18535	1			T1	1		T2	231		T69	1
valid_sources[0x34]	18448	1			T4	5		T2	233		T3	10
valid_sources[0x35]	19479	1			T4	1		T5	1		T2	239
valid_sources[0x36]	18217	1			T8	2		T4	5		T1	5
valid_sources[0x37]	17350	1			T4	8		T1	5		T5	3
valid_sources[0x38]	15676	1			T4	7		T1	1		T17	2
valid_sources[0x39]	17445	1			T4	10		T1	2		T5	1
valid_sources[0x3a]	17874	1			T4	3		T5	1		T2	238
valid_sources[0x3b]	17289	1			T4	2		T5	2		T2	253
valid_sources[0x3c]	16519	1			T4	1		T1	2		T2	240
valid_sources[0x3d]	17960	1			T24	1		T5	2		T2	265
valid_sources[0x3e]	17281	1			T4	2		T1	4		T5	1
valid_sources[0x3f]	17924	1			T4	2		T1	4		T5	1
valid_sources[0x40]	17068	1			T24	2		T1	4		T17	1
valid_sources[0x41]	16323	1			T4	1		T1	1		T5	3
valid_sources[0x42]	15896	1			T4	3		T5	2		T2	234
valid_sources[0x43]	18629	1			T1	1		T5	1		T2	226
valid_sources[0x44]	17782	1			T4	1		T1	1		T20	1
valid_sources[0x45]	17501	1			T25	1		T1	1		T5	1
valid_sources[0x46]	18351	1			T1	1		T5	1		T2	243
valid_sources[0x47]	16507	1			T4	4		T2	210		T3	5
valid_sources[0x48]	16836	1			T4	3		T5	1		T2	236
valid_sources[0x49]	18594	1			T4	2		T2	240		T37	2
valid_sources[0x4a]	18265	1			T4	6		T1	2		T5	4
valid_sources[0x4b]	18754	1			T1	1		T5	2		T2	224
valid_sources[0x4c]	16781	1			T4	1		T1	3		T5	1
valid_sources[0x4d]	16732	1			T1	1		T5	2		T2	225
valid_sources[0x4e]	16221	1			T1	1		T20	1		T5	5
valid_sources[0x4f]	17581	1			T1	2		T2	243		T3	4
valid_sources[0x50]	16923	1			T1	1		T2	259		T3	6
valid_sources[0x51]	17028	1			T1	1		T17	1		T5	1
valid_sources[0x52]	16803	1			T7	1		T4	1		T1	2
valid_sources[0x53]	17007	1			T25	3		T4	2		T1	3
valid_sources[0x54]	17301	1			T4	3		T1	2		T5	1
valid_sources[0x55]	17315	1			T4	5		T1	2		T5	2
valid_sources[0x56]	18164	1			T4	2		T5	1		T2	218
valid_sources[0x57]	18198	1			T4	4		T17	1		T5	1
valid_sources[0x58]	17970	1			T25	3		T1	1		T5	1
valid_sources[0x59]	18442	1			T4	6		T1	4		T5	1
valid_sources[0x5a]	16664	1			T4	1		T1	2		T5	1
valid_sources[0x5b]	18057	1			T4	2		T1	3		T5	1
valid_sources[0x5c]	18112	1			T4	6		T1	1		T5	1
valid_sources[0x5d]	18013	1			T20	2		T5	1		T2	275
valid_sources[0x5e]	16802	1			T4	3		T1	1		T5	1
valid_sources[0x5f]	17361	1			T4	1		T1	3		T20	1
valid_sources[0x60]	17912	1			T24	1		T1	1		T5	1
valid_sources[0x61]	18050	1			T24	1		T1	1		T2	233
valid_sources[0x62]	17422	1			T1	4		T20	2		T2	251
valid_sources[0x63]	16717	1			T4	1		T1	1		T20	1
valid_sources[0x64]	16802	1			T4	2		T1	4		T20	1
valid_sources[0x65]	17021	1			T4	12		T1	2		T5	2
valid_sources[0x66]	18406	1			T7	2		T25	6		T1	1
valid_sources[0x67]	15531	1			T1	1		T5	1		T2	253
valid_sources[0x68]	18585	1			T1	1		T5	2		T2	221
valid_sources[0x69]	17462	1			T1	1		T17	2		T5	5
valid_sources[0x6a]	17212	1			T4	3		T1	1		T5	1
valid_sources[0x6b]	17722	1			T4	5		T2	238		T37	1
valid_sources[0x6c]	15972	1			T25	1		T4	3		T1	1
valid_sources[0x6d]	17360	1			T4	1		T5	3		T2	229
valid_sources[0x6e]	17086	1			T4	4		T5	1		T2	242
valid_sources[0x6f]	16184	1			T4	1		T1	3		T5	1
valid_sources[0x70]	16383	1			T5	2		T2	270		T3	15
valid_sources[0x71]	16786	1			T8	1		T5	1		T2	237
valid_sources[0x72]	18676	1			T4	3		T20	1		T5	3
valid_sources[0x73]	17378	1			T4	7		T1	3		T5	1
valid_sources[0x74]	17620	1			T4	6		T2	243		T3	9
valid_sources[0x75]	16608	1			T1	1		T5	1		T2	250
valid_sources[0x76]	19069	1			T4	3		T5	1		T2	222
valid_sources[0x77]	18149	1			T24	1		T4	1		T5	3
valid_sources[0x78]	17842	1			T5	1		T2	260		T3	16
valid_sources[0x79]	17105	1			T24	1		T4	1		T1	1
valid_sources[0x7a]	17709	1			T7	1		T5	4		T2	227
valid_sources[0x7b]	17372	1			T4	3		T26	4		T17	1
valid_sources[0x7c]	18253	1			T4	2		T1	2		T5	1
valid_sources[0x7d]	18311	1			T5	2		T2	255		T33	1
valid_sources[0x7e]	17514	1			T4	1		T2	257		T3	4
valid_sources[0x7f]	16947	1			T24	1		T2	221		T22	1
valid_sources[0x80]	16363	1			T4	1		T5	4		T2	240

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

961457

1

T6

5

T7

7

T8

1

values[0x0]

all_enables

biggest_size

1451007

1

T6

2

T7

5

T24

1

values[0x1]

all_enables

biggest_size

1402556

1

T7

1

T25

7

T4

44