Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
379798 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
235778174 |
1 |
|
|
T6 |
2012 |
|
T7 |
888 |
|
T8 |
1989 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9098 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
236148874 |
1 |
|
|
T6 |
2012 |
|
T7 |
888 |
|
T8 |
1989 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
136311939 |
1 |
|
|
T6 |
1821 |
|
T7 |
326 |
|
T8 |
1991 |
auto[1] |
99846033 |
1 |
|
|
T6 |
193 |
|
T7 |
564 |
|
T24 |
7 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5628 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T18 |
2 |
auto[0] |
auto[1] |
auto[0] |
308144 |
1 |
|
|
T25 |
2 |
|
T26 |
145 |
|
T2 |
306 |
auto[0] |
auto[1] |
auto[1] |
64506 |
1 |
|
|
T26 |
134 |
|
T2 |
407 |
|
T3 |
180 |
auto[1] |
auto[1] |
auto[0] |
135996217 |
1 |
|
|
T6 |
1819 |
|
T7 |
324 |
|
T8 |
1989 |
auto[1] |
auto[1] |
auto[1] |
99780007 |
1 |
|
|
T6 |
193 |
|
T7 |
564 |
|
T24 |
5 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183986 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
117893146 |
1 |
|
|
T6 |
1004 |
|
T7 |
441 |
|
T8 |
993 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8142 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
118068990 |
1 |
|
|
T6 |
1004 |
|
T7 |
441 |
|
T8 |
993 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
68154024 |
1 |
|
|
T6 |
910 |
|
T7 |
163 |
|
T8 |
995 |
auto[1] |
49923108 |
1 |
|
|
T6 |
96 |
|
T7 |
280 |
|
T24 |
4 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5628 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T18 |
2 |
auto[0] |
auto[1] |
auto[0] |
143487 |
1 |
|
|
T25 |
1 |
|
T26 |
96 |
|
T2 |
155 |
auto[0] |
auto[1] |
auto[1] |
33351 |
1 |
|
|
T26 |
67 |
|
T2 |
198 |
|
T3 |
92 |
auto[1] |
auto[1] |
auto[0] |
68003915 |
1 |
|
|
T6 |
908 |
|
T7 |
161 |
|
T8 |
993 |
auto[1] |
auto[1] |
auto[1] |
49888237 |
1 |
|
|
T6 |
96 |
|
T7 |
280 |
|
T24 |
2 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
701100 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
471033621 |
1 |
|
|
T6 |
3659 |
|
T7 |
1692 |
|
T8 |
3933 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11065 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
471723656 |
1 |
|
|
T6 |
3659 |
|
T7 |
1692 |
|
T8 |
3933 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
272042575 |
1 |
|
|
T6 |
3277 |
|
T7 |
570 |
|
T8 |
3935 |
auto[1] |
199692146 |
1 |
|
|
T6 |
384 |
|
T7 |
1124 |
|
T24 |
15 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5628 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T18 |
2 |
auto[0] |
auto[1] |
auto[0] |
563443 |
1 |
|
|
T25 |
4 |
|
T26 |
275 |
|
T2 |
688 |
auto[0] |
auto[1] |
auto[1] |
130509 |
1 |
|
|
T26 |
282 |
|
T2 |
849 |
|
T3 |
356 |
auto[1] |
auto[1] |
auto[0] |
271469587 |
1 |
|
|
T6 |
3275 |
|
T7 |
568 |
|
T8 |
3933 |
auto[1] |
auto[1] |
auto[1] |
199560117 |
1 |
|
|
T6 |
384 |
|
T7 |
1124 |
|
T24 |
13 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
371635 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
241225447 |
1 |
|
|
T6 |
1829 |
|
T7 |
845 |
|
T8 |
1966 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8672 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[1] |
241588410 |
1 |
|
|
T6 |
1829 |
|
T7 |
845 |
|
T8 |
1966 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
139379883 |
1 |
|
|
T6 |
1640 |
|
T7 |
284 |
|
T8 |
1968 |
auto[1] |
102217199 |
1 |
|
|
T6 |
191 |
|
T7 |
563 |
|
T24 |
7 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5614 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
1534 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T18 |
2 |
auto[0] |
auto[1] |
auto[0] |
297045 |
1 |
|
|
T25 |
2 |
|
T26 |
144 |
|
T2 |
307 |
auto[0] |
auto[1] |
auto[1] |
67442 |
1 |
|
|
T26 |
134 |
|
T2 |
422 |
|
T3 |
199 |
auto[1] |
auto[1] |
auto[0] |
139075700 |
1 |
|
|
T6 |
1638 |
|
T7 |
282 |
|
T8 |
1966 |
auto[1] |
auto[1] |
auto[1] |
102148223 |
1 |
|
|
T6 |
191 |
|
T7 |
563 |
|
T24 |
5 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |