Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	100.00	1	100	1	64	64
TransHmac	100.00	1	100	1	64	64
TransKmac	100.00	1	100	1	64	64
TransOtbn	100.00	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1541168

1

T6

2

T7

2

T8

2

auto[1]

501221122

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

434980851

1

T6

824

T7

255

T8

522

auto[1]

67781439

1

T6

2989

T7

1509

T8

3577

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10177

1

T6

2

T7

2

T8

2

auto[1]

502752113

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289954311

1

T6

3413

T7

595

T8

4099

auto[1]

212807979

1

T6

400

T7

1169

T24

15

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2880

1

T13

2

T38

200

T60

2

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T62

2

T87

2

T160

2

auto[0]

auto[1]

auto[0]

auto[0]

472972

1

T25

170

T2

4525

T21

272

auto[0]

auto[1]

auto[0]

auto[1]

560132

1

T2

1181

T21

259

T23

29

auto[0]

auto[1]

auto[1]

auto[0]

418950

1

T2

4213

T23

163

T3

674

auto[0]

auto[1]

auto[1]

auto[1]

81966

1

T2

725

T23

28

T3

94

auto[1]

auto[1]

auto[0]

auto[0]

234896666

1

T6

422

T7

217

T8

520

auto[1]

auto[1]

auto[0]

auto[1]

54015898

1

T6

2989

T7

376

T8

3577

auto[1]

auto[1]

auto[1]

auto[0]

199186291

1

T6

400

T7

36

T24

13

auto[1]

auto[1]

auto[1]

auto[1]

13119238

1

T7

1133

T20

392

T2

5669

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1456038

1

T6

2

T7

2

T8

2

auto[1]

501306252

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445359247

1

T6

50

T7

1520

T8

3660

auto[1]

57403043

1

T6

3763

T7

244

T8

439

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10177

1

T6

2

T7

2

T8

2

auto[1]

502752113

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289954311

1

T6

3413

T7

595

T8

4099

auto[1]

212807979

1

T6

400

T7

1169

T24

15

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2880

1

T13

2

T38

200

T63

2

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T2

2

T87

4

T161

2

auto[0]

auto[1]

auto[0]

auto[0]

434319

1

T25

131

T2

5807

T21

977

auto[0]

auto[1]

auto[0]

auto[1]

538006

1

T2

1117

T21

261

T23

25

auto[0]

auto[1]

auto[1]

auto[0]

392392

1

T2

4610

T21

177

T23

134

auto[0]

auto[1]

auto[1]

auto[1]

84173

1

T2

898

T23

57

T3

94

auto[1]

auto[1]

auto[0]

auto[0]

240112966

1

T6

48

T7

349

T8

3658

auto[1]

auto[1]

auto[0]

auto[1]

48860377

1

T6

3363

T7

244

T8

439

auto[1]

auto[1]

auto[1]

auto[0]

204413735

1

T7

1169

T24

13

T26

379

auto[1]

auto[1]

auto[1]

auto[1]

7916145

1

T6

400

T20

262

T2

189176

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1396074

1

T6

2

T7

2

T8

2

auto[1]

501366216

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

447277535

1

T6

716

T7

1592

T8

3660

auto[1]

55484755

1

T6

3097

T7

172

T8

439

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10177

1

T6

2

T7

2

T8

2

auto[1]

502752113

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289954311

1

T6

3413

T7

595

T8

4099

auto[1]

212807979

1

T6

400

T7

1169

T24

15

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2884

1

T13

4

T38

200

T60

2

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T2

2

T87

4

T160

2

auto[0]

auto[1]

auto[0]

auto[0]

388550

1

T25

89

T2

4088

T21

1070

auto[0]

auto[1]

auto[0]

auto[1]

562805

1

T2

1236

T21

345

T23

25

auto[0]

auto[1]

auto[1]

auto[0]

353114

1

T2

4663

T21

177

T23

226

auto[0]

auto[1]

auto[1]

auto[1]

84457

1

T2

733

T23

28

T3

188

auto[1]

auto[1]

auto[0]

auto[0]

244920226

1

T6

509

T7

457

T8

3658

auto[1]

auto[1]

auto[0]

auto[1]

44074087

1

T6

2902

T7

136

T8

439

auto[1]

auto[1]

auto[1]

auto[0]

201609921

1

T6

205

T7

1133

T24

13

auto[1]

auto[1]

auto[1]

auto[1]

10758953

1

T6

195

T7

36

T20

182

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1321450

1

T6

2

T7

2

T8

2

auto[1]

501440840

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

436320523

1

T6

3263

T7

253

T8

3660

auto[1]

66441767

1

T6

550

T7

1511

T8

439

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10177

1

T6

2

T7

2

T8

2

auto[1]

502752113

1

T6

3811

T7

1762

T8

4097

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289954311

1

T6

3413

T7

595

T8

4099

auto[1]

212807979

1

T6

400

T7

1169

T24

15

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2884

1

T13

4

T38

200

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T2

2

T62

2

T87

2

auto[0]

auto[1]

auto[0]

auto[0]

329908

1

T25

43

T2

4995

T21

983

auto[0]

auto[1]

auto[0]

auto[1]

594825

1

T2

1178

T21

432

T23

85

auto[0]

auto[1]

auto[1]

auto[0]

305916

1

T2

4146

T23

120

T3

584

auto[0]

auto[1]

auto[1]

auto[1]

83653

1

T2

1220

T3

376

T109

127

auto[1]

auto[1]

auto[0]

auto[0]

237169351

1

T6

3066

T7

251

T8

3658

auto[1]

auto[1]

auto[0]

auto[1]

51851584

1

T6

345

T7

342

T8

439

auto[1]

auto[1]

auto[1]

auto[0]

198509874

1

T6

195

T24

13

T26

379

auto[1]

auto[1]

auto[1]

auto[1]

13907002

1

T6

205

T7

1169

T20

174

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded