Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T4,T26
0	1	Covered	T26,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T26
1	0	Covered	T19,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1069815547	13961	0	0
GateOpen_A	1069815547	20864	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1069815547	13961	0	0
T1	357598	0	0	0
T2	1198620	96	0	0
T3	0	61	0	0
T4	127881	0	0	0
T5	99514	0	0	0
T10	0	27	0	0
T17	9409	0	0	0
T18	5519	0	0	0
T19	3630	4	0	0
T20	10522	0	0	0
T25	4565	4	0	0
T26	33140	10	0	0
T35	0	12	0	0
T37	0	4	0	0
T110	0	4	0	0
T154	0	32	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1069815547	20864	0	0
T1	357598	0	0	0
T4	127881	48	0	0
T5	0	24	0	0
T6	8675	4	0	0
T7	4106	4	0	0
T8	9268	4	0	0
T17	9409	4	0	0
T18	5519	0	0	0
T19	0	8	0	0
T20	0	4	0	0
T24	4307	0	0	0
T25	4565	8	0	0
T26	33140	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T4,T26
0	1	Covered	T26,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T26
1	0	Covered	T19,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	117959201	3294	0	0
GateOpen_A	117959201	5019	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117959201	3294	0	0
T1	39724	0	0	0
T2	132399	21	0	0
T3	0	14	0	0
T4	9163	0	0	0
T5	8805	0	0	0
T10	0	7	0	0
T17	1096	0	0	0
T18	605	0	0	0
T19	389	1	0	0
T20	1548	0	0	0
T25	494	1	0	0
T26	3676	2	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117959201	5019	0	0
T1	39724	0	0	0
T4	9163	12	0	0
T5	0	6	0	0
T6	1020	1	0	0
T7	461	1	0	0
T8	1020	1	0	0
T17	1096	1	0	0
T18	605	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T24	487	0	0	0
T25	494	2	0	0
T26	3676	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T4,T26
0	1	Covered	T26,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T26
1	0	Covered	T19,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	235919232	3579	0	0
GateOpen_A	235919232	5304	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235919232	3579	0	0
T1	79448	0	0	0
T2	264799	25	0	0
T3	0	15	0	0
T4	18327	0	0	0
T5	17608	0	0	0
T10	0	6	0	0
T17	2191	0	0	0
T18	1209	0	0	0
T19	777	1	0	0
T20	3095	0	0	0
T25	988	1	0	0
T26	7352	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235919232	5304	0	0
T1	79448	0	0	0
T4	18327	12	0	0
T5	0	6	0	0
T6	2042	1	0	0
T7	922	1	0	0
T8	2039	1	0	0
T17	2191	1	0	0
T18	1209	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T24	975	0	0	0
T25	988	2	0	0
T26	7352	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T4,T26
0	1	Covered	T26,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T26
1	0	Covered	T19,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	473450160	3546	0	0
GateOpen_A	473450160	5272	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473450160	3546	0	0
T1	158948	0	0	0
T2	530049	24	0	0
T3	0	16	0	0
T4	66926	0	0	0
T5	48733	0	0	0
T10	0	8	0	0
T17	4081	0	0	0
T18	2470	0	0	0
T19	1633	1	0	0
T20	3920	0	0	0
T25	2055	1	0	0
T26	14741	2	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473450160	5272	0	0
T1	158948	0	0	0
T4	66926	12	0	0
T5	0	6	0	0
T6	3742	1	0	0
T7	1815	1	0	0
T8	4139	1	0	0
T17	4081	1	0	0
T18	2470	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T24	1897	0	0	0
T25	2055	2	0	0
T26	14741	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T4,T26
0	1	Covered	T26,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T26
1	0	Covered	T19,T35,T36
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	242486954	3542	0	0
GateOpen_A	242486954	5269	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486954	3542	0	0
T1	79478	0	0	0
T2	271373	26	0	0
T3	0	16	0	0
T4	33465	0	0	0
T5	24368	0	0	0
T10	0	6	0	0
T17	2041	0	0	0
T18	1235	0	0	0
T19	831	1	0	0
T20	1959	0	0	0
T25	1028	1	0	0
T26	7371	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486954	5269	0	0
T1	79478	0	0	0
T4	33465	12	0	0
T5	0	6	0	0
T6	1871	1	0	0
T7	908	1	0	0
T8	2070	1	0	0
T17	2041	1	0	0
T18	1235	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T24	948	0	0	0
T25	1028	2	0	0
T26	7371	4	0	0