Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	848561265	82419	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	848561265	82419	0	0
T1	206965	144	0	0
T2	1290955	844	0	0
T3	0	326	0	0
T5	60915	0	0	0
T10	0	215	0	0
T11	0	179	0	0
T12	0	158	0	0
T13	0	1575	0	0
T14	0	209	0	0
T15	0	432	0	0
T16	0	299	0	0
T17	5950	0	0	0
T18	6300	0	0	0
T19	4410	0	0	0
T20	10005	0	0	0
T21	9925	0	0	0
T22	7475	0	0	0
T23	14165	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169712253	11940	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	11940	0	0
T1	41393	23	0	0
T2	258191	123	0	0
T3	0	52	0	0
T5	12183	0	0	0
T10	0	28	0	0
T11	0	25	0	0
T12	0	25	0	0
T13	0	201	0	0
T14	0	27	0	0
T15	0	57	0	0
T16	0	39	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169712253	11912	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	11912	0	0
T1	41393	23	0	0
T2	258191	123	0	0
T3	0	51	0	0
T5	12183	0	0	0
T10	0	27	0	0
T11	0	24	0	0
T12	0	25	0	0
T13	0	226	0	0
T14	0	27	0	0
T15	0	57	0	0
T16	0	44	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169712253	16576	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	16576	0	0
T1	41393	29	0	0
T2	258191	172	0	0
T3	0	66	0	0
T5	12183	0	0	0
T10	0	46	0	0
T11	0	36	0	0
T12	0	33	0	0
T13	0	312	0	0
T14	0	41	0	0
T15	0	87	0	0
T16	0	58	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169712253	16506	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	16506	0	0
T1	41393	29	0	0
T2	258191	168	0	0
T3	0	66	0	0
T5	12183	0	0	0
T10	0	43	0	0
T11	0	35	0	0
T12	0	31	0	0
T13	0	312	0	0
T14	0	43	0	0
T15	0	87	0	0
T16	0	57	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169712253	25485	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	25485	0	0
T1	41393	40	0	0
T2	258191	258	0	0
T3	0	91	0	0
T5	12183	0	0	0
T10	0	71	0	0
T11	0	59	0	0
T12	0	44	0	0
T13	0	524	0	0
T14	0	71	0	0
T15	0	144	0	0
T16	0	101	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0