Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T5,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	169712253	166945626	0	0
AllClkBypReqTrue_A	169712253	132528	0	0
IoClkBypReqFalse_A	169712253	166861769	0	2415
IoClkBypReqTrue_A	169712253	211621	0	0
LcClkBypAckFalse_A	169712253	166951698	0	0
LcClkBypAckTrue_A	169712253	126456	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	166945626	0	0
T1	41393	41343	0	0
T4	69716	5646	0	0
T6	1480	1448	0	0
T7	1797	1626	0	0
T8	775	736	0	0
T17	1190	1134	0	0
T18	1260	1163	0	0
T24	1917	1645	0	0
T25	2054	1850	0	0
T26	767	760	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	132528	0	0
T1	41393	0	0	0
T2	0	1037	0	0
T4	69716	0	0	0
T7	1797	50	0	0
T8	775	0	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	0	44	0	0
T22	0	12	0	0
T24	1917	65	0	0
T25	2054	0	0	0
T26	767	0	0	0
T66	0	33	0	0
T67	0	347	0	0
T68	0	235	0	0
T69	0	66	0	0
T108	0	63	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	166861769	0	2415
T1	41393	41341	0	3
T4	69716	5622	0	3
T6	1480	1242	0	3
T7	1797	1674	0	3
T8	775	691	0	3
T17	1190	983	0	3
T18	1260	1161	0	3
T24	1917	1501	0	3
T25	2054	1848	0	3
T26	767	758	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	211621	0	0
T1	41393	0	0	0
T2	0	1655	0	0
T4	69716	0	0	0
T6	1480	204	0	0
T7	1797	0	0	0
T8	775	43	0	0
T17	1190	149	0	0
T18	1260	0	0	0
T20	0	28	0	0
T24	1917	207	0	0
T25	2054	0	0	0
T26	767	0	0	0
T66	0	144	0	0
T67	0	522	0	0
T68	0	452	0	0
T108	0	136	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	166951698	0	0
T1	41393	41343	0	0
T4	69716	5646	0	0
T6	1480	1313	0	0
T7	1797	1676	0	0
T8	775	730	0	0
T17	1190	1031	0	0
T18	1260	1163	0	0
T24	1917	1568	0	0
T25	2054	1850	0	0
T26	767	760	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	126456	0	0
T1	41393	0	0	0
T2	0	1034	0	0
T4	69716	0	0	0
T6	1480	135	0	0
T7	1797	0	0	0
T8	775	6	0	0
T17	1190	103	0	0
T18	1260	0	0	0
T24	1917	142	0	0
T25	2054	0	0	0
T26	767	0	0	0
T66	0	70	0	0
T67	0	285	0	0
T68	0	369	0	0
T70	0	245	0	0
T108	0	45	0	0