Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2018462852	15302	0	0
TransStop_A	2018462852	7806	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2018462852	15302	0	0
T1	662304	0	0	0
T2	2259008	212	0	0
T3	0	40	0	0
T4	278868	0	0	0
T5	203060	0	0	0
T10	0	54	0	0
T17	17004	0	0	0
T18	10288	0	0	0
T19	7092	0	0	0
T20	16332	0	0	0
T21	0	28	0	0
T23	0	27	0	0
T25	8560	4	0	0
T26	61424	0	0	0
T37	0	4	0	0
T81	0	10	0	0
T82	0	37	0	0
T109	0	38	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2018462852	7806	0	0
T1	662304	0	0	0
T2	2259008	107	0	0
T3	0	21	0	0
T4	278868	0	0	0
T5	203060	0	0	0
T10	0	14	0	0
T17	17004	0	0	0
T18	10288	0	0	0
T19	7092	0	0	0
T20	16332	0	0	0
T21	0	26	0	0
T23	0	15	0	0
T25	8560	4	0	0
T26	61424	0	0	0
T37	0	4	0	0
T81	0	5	0	0
T82	0	34	0	0
T109	0	21	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504615713	3781	0	0
TransStop_A	504615713	1949	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	3781	0	0
T1	165576	0	0	0
T2	564752	45	0	0
T3	0	9	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	17	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	3	0	0
T23	0	5	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	10	0	0
T109	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	1949	0	0
T1	165576	0	0	0
T2	564752	22	0	0
T3	0	5	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	5	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	3	0	0
T23	0	2	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	2	0	0
T82	0	10	0	0
T109	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504615713	3834	0	0
TransStop_A	504615713	1941	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	3834	0	0
T1	165576	0	0	0
T2	564752	57	0	0
T3	0	13	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	9	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	7	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	1	0	0
T82	0	9	0	0
T109	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	1941	0	0
T1	165576	0	0	0
T2	564752	30	0	0
T3	0	8	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	2	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	7	0	0
T23	0	4	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T82	0	7	0	0
T109	0	7	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504615713	3861	0	0
TransStop_A	504615713	1971	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	3861	0	0
T1	165576	0	0	0
T2	564752	51	0	0
T3	0	9	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	15	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	9	0	0
T23	0	8	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	9	0	0
T109	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	1971	0	0
T1	165576	0	0	0
T2	564752	24	0	0
T3	0	4	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	4	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	4	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	1	0	0
T82	0	8	0	0
T109	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504615713	3826	0	0
TransStop_A	504615713	1945	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	3826	0	0
T1	165576	0	0	0
T2	564752	59	0	0
T3	0	9	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	13	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	7	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	9	0	0
T109	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615713	1945	0	0
T1	165576	0	0	0
T2	564752	31	0	0
T3	0	4	0	0
T4	69717	0	0	0
T5	50765	0	0	0
T10	0	3	0	0
T17	4251	0	0	0
T18	2572	0	0	0
T19	1773	0	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	5	0	0
T25	2140	1	0	0
T26	15356	0	0	0
T37	0	1	0	0
T81	0	2	0	0
T82	0	9	0	0
T109	0	5	0	0