SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 339424506 | 334161072 | 0 | 0 |
gen_flops.OutputDelay_A | 339424506 | 334146426 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T24 | 2 | 2 | 0 | 0 |
T25 | 2 | 2 | 0 | 0 |
T26 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 339424506 | 334161072 | 0 | 0 |
T1 | 82786 | 82688 | 0 | 0 |
T4 | 139432 | 11316 | 0 | 0 |
T6 | 2960 | 2898 | 0 | 0 |
T7 | 3594 | 3354 | 0 | 0 |
T8 | 1550 | 1474 | 0 | 0 |
T17 | 2380 | 2270 | 0 | 0 |
T18 | 2520 | 2328 | 0 | 0 |
T24 | 3834 | 3422 | 0 | 0 |
T25 | 4108 | 3702 | 0 | 0 |
T26 | 1534 | 1522 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 339424506 | 334146426 | 0 | 4830 |
T1 | 82786 | 82682 | 0 | 6 |
T4 | 139432 | 11222 | 0 | 6 |
T6 | 2960 | 2892 | 0 | 6 |
T7 | 3594 | 3348 | 0 | 6 |
T8 | 1550 | 1468 | 0 | 6 |
T17 | 2380 | 2264 | 0 | 6 |
T18 | 2520 | 2322 | 0 | 6 |
T24 | 3834 | 3416 | 0 | 6 |
T25 | 4108 | 3696 | 0 | 6 |
T26 | 1534 | 1516 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 169712253 | 167080536 | 0 | 0 |
gen_flops.OutputDelay_A | 169712253 | 167073213 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169712253 | 167080536 | 0 | 0 |
T1 | 41393 | 41344 | 0 | 0 |
T4 | 69716 | 5658 | 0 | 0 |
T6 | 1480 | 1449 | 0 | 0 |
T7 | 1797 | 1677 | 0 | 0 |
T8 | 775 | 737 | 0 | 0 |
T17 | 1190 | 1135 | 0 | 0 |
T18 | 1260 | 1164 | 0 | 0 |
T24 | 1917 | 1711 | 0 | 0 |
T25 | 2054 | 1851 | 0 | 0 |
T26 | 767 | 761 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169712253 | 167073213 | 0 | 2415 |
T1 | 41393 | 41341 | 0 | 3 |
T4 | 69716 | 5611 | 0 | 3 |
T6 | 1480 | 1446 | 0 | 3 |
T7 | 1797 | 1674 | 0 | 3 |
T8 | 775 | 734 | 0 | 3 |
T17 | 1190 | 1132 | 0 | 3 |
T18 | 1260 | 1161 | 0 | 3 |
T24 | 1917 | 1708 | 0 | 3 |
T25 | 2054 | 1848 | 0 | 3 |
T26 | 767 | 758 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 169712253 | 167080536 | 0 | 0 |
gen_flops.OutputDelay_A | 169712253 | 167073213 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169712253 | 167080536 | 0 | 0 |
T1 | 41393 | 41344 | 0 | 0 |
T4 | 69716 | 5658 | 0 | 0 |
T6 | 1480 | 1449 | 0 | 0 |
T7 | 1797 | 1677 | 0 | 0 |
T8 | 775 | 737 | 0 | 0 |
T17 | 1190 | 1135 | 0 | 0 |
T18 | 1260 | 1164 | 0 | 0 |
T24 | 1917 | 1711 | 0 | 0 |
T25 | 2054 | 1851 | 0 | 0 |
T26 | 767 | 761 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169712253 | 167073213 | 0 | 2415 |
T1 | 41393 | 41341 | 0 | 3 |
T4 | 69716 | 5611 | 0 | 3 |
T6 | 1480 | 1446 | 0 | 3 |
T7 | 1797 | 1674 | 0 | 3 |
T8 | 775 | 734 | 0 | 3 |
T17 | 1190 | 1132 | 0 | 3 |
T18 | 1260 | 1161 | 0 | 3 |
T24 | 1917 | 1708 | 0 | 3 |
T25 | 2054 | 1848 | 0 | 3 |
T26 | 767 | 758 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |