Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	169712253	16812371	0	63

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	16812371	0	63
T1	41393	9758	0	1
T2	258191	75986	0	0
T3	0	23808	0	1
T5	12183	0	0	0
T10	0	23881	0	0
T11	0	19829	0	1
T12	0	10855	0	1
T13	0	185957	0	0
T14	0	25890	0	1
T15	0	45426	0	0
T16	0	0	0	1
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T27	0	797	0	1
T111	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1