Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	170731694	5620272	0	0
clk_enables_rd_A	170731694	52446	0	0
clk_hints_rd_A	170731694	45232	0	0
extclk_ctrl_rd_A	170731694	56006	0	0
extclk_ctrl_regwen_rd_A	170731694	44004	0	0
jitter_enable_rd_A	170731694	62494	0	0
jitter_regwen_rd_A	170731694	48456	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	5620272	0	0
T2	258191	81109	0	0
T10	0	66184	0	0
T13	0	181546	0	0
T15	0	58128	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T37	988	0	0	0
T60	0	184923	0	0
T61	0	89961	0	0
T62	0	161600	0	0
T63	0	54987	0	0
T64	0	62697	0	0
T65	0	79530	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T68	1950	0	0	0
T69	1577	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	52446	0	0
T2	258191	1508	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T37	988	0	0	0
T61	0	3671	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T68	1950	0	0	0
T69	1577	0	0	0
T87	0	2832	0	0
T127	0	1	0	0
T128	0	8	0	0
T129	0	4	0	0
T130	0	2	0	0
T131	0	4225	0	0
T132	0	773	0	0
T133	0	1641	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	45232	0	0
T2	258191	1532	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T37	988	0	0	0
T61	0	3353	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T68	1950	0	0	0
T69	1577	0	0	0
T87	0	2369	0	0
T128	0	4	0	0
T131	0	3329	0	0
T132	0	575	0	0
T133	0	1474	0	0
T134	0	10	0	0
T135	0	3	0	0
T136	0	4788	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	56006	0	0
T1	41393	0	0	0
T2	0	1662	0	0
T4	69716	0	0	0
T5	12183	43	0	0
T17	1190	26	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T24	1917	18	0	0
T25	2054	0	0	0
T26	767	0	0	0
T44	0	16	0	0
T79	0	21	0	0
T83	0	5	0	0
T137	0	33	0	0
T138	0	57	0	0
T139	0	20	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	44004	0	0
T2	258191	1511	0	0
T5	12183	22	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T61	0	2938	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T68	1950	0	0	0
T69	1577	0	0	0
T87	0	2572	0	0
T131	0	3465	0	0
T132	0	573	0	0
T133	0	1404	0	0
T140	0	50	0	0
T141	0	24	0	0
T142	0	23	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	62494	0	0
T2	258191	1544	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T37	988	0	0	0
T61	0	4817	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T68	1950	0	0	0
T69	1577	0	0	0
T87	0	3064	0	0
T127	0	124	0	0
T128	0	109	0	0
T129	0	130	0	0
T130	0	74	0	0
T131	0	4013	0	0
T132	0	799	0	0
T133	0	2903	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	48456	0	0
T2	258191	1711	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T37	988	0	0	0
T61	0	3414	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T68	1950	0	0	0
T69	1577	0	0	0
T87	0	2879	0	0
T131	0	3641	0	0
T132	0	541	0	0
T133	0	1824	0	0
T136	0	5762	0	0
T143	0	2053	0	0
T144	0	4403	0	0
T145	0	4965	0	0