Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	509136759	481	0	0
StatusRise_A	509136759	481	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509136759	481	0	0
T2	774573	0	0	0
T5	36549	0	0	0
T19	2646	3	0	0
T20	6003	0	0	0
T21	5955	0	0	0
T22	4485	0	0	0
T23	8499	0	0	0
T32	3936	0	0	0
T35	0	11	0	0
T36	0	5	0	0
T43	0	8	0	0
T66	5937	0	0	0
T67	7305	0	0	0
T146	0	11	0	0
T147	0	18	0	0
T148	0	1	0	0
T149	0	12	0	0
T150	0	3	0	0
T151	0	16	0	0
T152	0	5	0	0
T153	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509136759	481	0	0
T2	774573	0	0	0
T5	36549	0	0	0
T19	2646	3	0	0
T20	6003	0	0	0
T21	5955	0	0	0
T22	4485	0	0	0
T23	8499	0	0	0
T32	3936	0	0	0
T35	0	11	0	0
T36	0	5	0	0
T43	0	8	0	0
T66	5937	0	0	0
T67	7305	0	0	0
T146	0	11	0	0
T147	0	18	0	0
T148	0	1	0	0
T149	0	12	0	0
T150	0	3	0	0
T151	0	16	0	0
T152	0	5	0	0
T153	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	169712253	163	0	0
StatusRise_A	169712253	163	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	163	0	0
T2	258191	0	0	0
T5	12183	0	0	0
T19	882	1	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	2	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T146	0	3	0	0
T147	0	8	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	163	0	0
T2	258191	0	0	0
T5	12183	0	0	0
T19	882	1	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	2	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T146	0	3	0	0
T147	0	8	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	169712253	160	0	0
StatusRise_A	169712253	160	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	160	0	0
T2	258191	0	0	0
T5	12183	0	0	0
T19	882	1	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	160	0	0
T2	258191	0	0	0
T5	12183	0	0	0
T19	882	1	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	169712253	158	0	0
StatusRise_A	169712253	158	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	158	0	0
T2	258191	0	0	0
T5	12183	0	0	0
T19	882	1	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	2	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T146	0	3	0	0
T147	0	6	0	0
T149	0	3	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169712253	158	0	0
T2	258191	0	0	0
T5	12183	0	0	0
T19	882	1	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T22	1495	0	0	0
T23	2833	0	0	0
T32	1312	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	2	0	0
T66	1979	0	0	0
T67	2435	0	0	0
T146	0	3	0	0
T147	0	6	0	0
T149	0	3	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	6	0	0