Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48360	0	0
CgEnOn_A	2147483647	38836	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48360	0	0
T1	1019899	3	0	0
T2	4851930	45	0	0
T4	406744	36	0	0
T5	421704	0	0	0
T6	8672	3	0	0
T7	4105	3	0	0
T8	9266	3	0	0
T17	26406	3	0	0
T18	15799	3	0	0
T19	15037	6	0	0
T20	38111	0	0	0
T21	35325	0	0	0
T22	6883	0	0	0
T23	13544	0	0	0
T24	4303	3	0	0
T25	13122	7	0	0
T26	94559	10	0	0
T32	24247	0	0	0
T35	0	20	0	0
T36	0	10	0	0
T43	0	20	0	0
T62	0	5	0	0
T66	10141	0	0	0
T67	22260	0	0	0
T146	0	25	0	0
T147	0	20	0	0
T149	0	25	0	0
T150	0	10	0	0
T151	0	35	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38836	0	0
T1	1019899	0	0	0
T2	6050550	171	0	0
T3	0	104	0	0
T4	406744	0	0	0
T5	521216	0	0	0
T10	0	47	0	0
T17	26406	0	0	0
T18	15799	0	0	0
T19	18666	9	0	0
T20	48630	0	0	0
T21	35325	3	0	0
T22	6883	0	0	0
T23	13544	5	0	0
T25	13122	4	0	0
T26	94559	7	0	0
T32	24247	0	0	0
T35	0	29	0	0
T36	0	10	0	0
T37	0	4	0	0
T43	0	20	0	0
T62	0	4	0	0
T66	10141	0	0	0
T67	22260	0	0	0
T110	0	3	0	0
T146	0	25	0	0
T147	0	20	0	0
T149	0	25	0	0
T150	0	10	0	0
T151	0	35	0	0
T152	0	3	0	0
T154	0	33	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	235918834	167	0	0
CgEnOn_A	235918834	167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235918834	167	0	0
T2	264799	0	0	0
T5	17607	0	0	0
T19	777	1	0	0
T20	3094	0	0	0
T21	3620	0	0	0
T22	696	0	0	0
T23	1356	0	0	0
T32	2474	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	1032	0	0	0
T67	2461	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235918834	167	0	0
T2	264799	0	0	0
T5	17607	0	0	0
T19	777	1	0	0
T20	3094	0	0	0
T21	3620	0	0	0
T22	696	0	0	0
T23	1356	0	0	0
T32	2474	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	1032	0	0	0
T67	2461	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	117958808	167	0	0
CgEnOn_A	117958808	167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	167	0	0
T2	132399	0	0	0
T5	8804	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T21	1810	0	0	0
T22	348	0	0	0
T23	678	0	0	0
T32	1237	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	516	0	0	0
T67	1228	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	167	0	0
T2	132399	0	0	0
T5	8804	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T21	1810	0	0	0
T22	348	0	0	0
T23	678	0	0	0
T32	1237	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	516	0	0	0
T67	1228	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	117958808	167	0	0
CgEnOn_A	117958808	167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	167	0	0
T2	132399	0	0	0
T5	8804	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T21	1810	0	0	0
T22	348	0	0	0
T23	678	0	0	0
T32	1237	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	516	0	0	0
T67	1228	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	167	0	0
T2	132399	0	0	0
T5	8804	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T21	1810	0	0	0
T22	348	0	0	0
T23	678	0	0	0
T32	1237	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	516	0	0	0
T67	1228	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	117958808	167	0	0
CgEnOn_A	117958808	167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	167	0	0
T2	132399	0	0	0
T5	8804	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T21	1810	0	0	0
T22	348	0	0	0
T23	678	0	0	0
T32	1237	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	516	0	0	0
T67	1228	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	167	0	0
T2	132399	0	0	0
T5	8804	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T21	1810	0	0	0
T22	348	0	0	0
T23	678	0	0	0
T32	1237	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	516	0	0	0
T67	1228	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473449721	167	0	0
CgEnOn_A	473449721	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473449721	167	0	0
T2	530049	0	0	0
T5	48733	0	0	0
T19	1633	1	0	0
T20	3919	0	0	0
T21	7333	0	0	0
T22	1435	0	0	0
T23	2833	0	0	0
T32	5040	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T62	0	1	0	0
T66	2110	0	0	0
T67	4497	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473449721	163	0	0
T2	530049	0	0	0
T5	48733	0	0	0
T19	1633	1	0	0
T20	3919	0	0	0
T21	7333	0	0	0
T22	1435	0	0	0
T23	2833	0	0	0
T32	5040	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	4	0	0
T66	2110	0	0	0
T67	4497	0	0	0
T146	0	5	0	0
T147	0	4	0	0
T149	0	5	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504615272	165	0	0
CgEnOn_A	504615272	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	165	0	0
T2	564752	0	0	0
T5	50764	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	7638	0	0	0
T22	1495	0	0	0
T23	2952	0	0	0
T32	5251	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	2	0	0
T66	2198	0	0	0
T67	4685	0	0	0
T146	0	3	0	0
T147	0	8	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	164	0	0
T2	564752	0	0	0
T5	50764	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	7638	0	0	0
T22	1495	0	0	0
T23	2952	0	0	0
T32	5251	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	2	0	0
T66	2198	0	0	0
T67	4685	0	0	0
T146	0	3	0	0
T147	0	8	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504615272	165	0	0
CgEnOn_A	504615272	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	165	0	0
T2	564752	0	0	0
T5	50764	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	7638	0	0	0
T22	1495	0	0	0
T23	2952	0	0	0
T32	5251	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	2	0	0
T66	2198	0	0	0
T67	4685	0	0	0
T146	0	3	0	0
T147	0	8	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	164	0	0
T2	564752	0	0	0
T5	50764	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	7638	0	0	0
T22	1495	0	0	0
T23	2952	0	0	0
T32	5251	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T43	0	2	0	0
T66	2198	0	0	0
T67	4685	0	0	0
T146	0	3	0	0
T147	0	8	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242486548	161	0	0
CgEnOn_A	242486548	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486548	161	0	0
T2	271373	0	0	0
T5	24368	0	0	0
T19	831	1	0	0
T20	1959	0	0	0
T21	3666	0	0	0
T22	718	0	0	0
T23	1417	0	0	0
T32	2520	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	2	0	0
T63	0	1	0	0
T66	1055	0	0	0
T67	2248	0	0	0
T146	0	3	0	0
T147	0	6	0	0
T149	0	3	0	0
T151	0	4	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486548	158	0	0
T2	271373	0	0	0
T5	24368	0	0	0
T19	831	1	0	0
T20	1959	0	0	0
T21	3666	0	0	0
T22	718	0	0	0
T23	1417	0	0	0
T32	2520	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T43	0	2	0	0
T66	1055	0	0	0
T67	2248	0	0	0
T146	0	3	0	0
T147	0	6	0	0
T149	0	3	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	117958808	7723	0	0
CgEnOn_A	117958808	5348	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	7723	0	0
T1	39724	1	0	0
T4	9163	12	0	0
T6	1020	1	0	0
T7	460	1	0	0
T8	1019	1	0	0
T17	1095	1	0	0
T18	604	1	0	0
T24	486	1	0	0
T25	494	2	0	0
T26	3676	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117958808	5348	0	0
T1	39724	0	0	0
T2	132399	43	0	0
T3	0	31	0	0
T4	9163	0	0	0
T5	8804	0	0	0
T10	0	16	0	0
T17	1095	0	0	0
T18	604	0	0	0
T19	388	1	0	0
T20	1547	0	0	0
T25	494	1	0	0
T26	3676	2	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	235918834	7791	0	0
CgEnOn_A	235918834	5416	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235918834	7791	0	0
T1	79447	1	0	0
T4	18327	12	0	0
T6	2041	1	0	0
T7	922	1	0	0
T8	2039	1	0	0
T17	2191	1	0	0
T18	1208	1	0	0
T24	974	1	0	0
T25	987	2	0	0
T26	7351	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235918834	5416	0	0
T1	79447	0	0	0
T2	264799	42	0	0
T3	0	32	0	0
T4	18327	0	0	0
T5	17607	0	0	0
T10	0	15	0	0
T17	2191	0	0	0
T18	1208	0	0	0
T19	777	1	0	0
T20	3094	0	0	0
T25	987	1	0	0
T26	7351	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473449721	7772	0	0
CgEnOn_A	473449721	5393	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473449721	7772	0	0
T1	158947	1	0	0
T4	66926	12	0	0
T6	3741	1	0	0
T7	1815	1	0	0
T8	4139	1	0	0
T17	4080	1	0	0
T18	2469	1	0	0
T24	1896	1	0	0
T25	2054	2	0	0
T26	14741	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473449721	5393	0	0
T1	158947	0	0	0
T2	530049	41	0	0
T3	0	32	0	0
T4	66926	0	0	0
T5	48733	0	0	0
T10	0	16	0	0
T17	4080	0	0	0
T18	2469	0	0	0
T19	1633	1	0	0
T20	3919	0	0	0
T25	2054	1	0	0
T26	14741	2	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T35,T36
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242486548	7786	0	0
CgEnOn_A	242486548	5404	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486548	7786	0	0
T1	79477	1	0	0
T4	33464	12	0	0
T6	1870	1	0	0
T7	908	1	0	0
T8	2069	1	0	0
T17	2040	1	0	0
T18	1234	1	0	0
T24	947	1	0	0
T25	1027	2	0	0
T26	7371	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242486548	5404	0	0
T1	79477	0	0	0
T2	271373	42	0	0
T3	0	29	0	0
T4	33464	0	0	0
T5	24368	0	0	0
T10	0	19	0	0
T17	2040	0	0	0
T18	1234	0	0	0
T19	831	1	0	0
T20	1959	0	0	0
T25	1027	1	0	0
T26	7371	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T110	0	1	0	0
T154	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Covered	T25,T2,T21
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504615272	3946	0	0
CgEnOn_A	504615272	3945	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	3946	0	0
T1	165576	0	0	0
T2	564752	45	0	0
T3	0	9	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	3	0	0
T23	0	5	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	3945	0	0
T1	165576	0	0	0
T2	564752	45	0	0
T3	0	9	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	3	0	0
T23	0	5	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Covered	T25,T2,T21
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504615272	3999	0	0
CgEnOn_A	504615272	3998	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	3999	0	0
T1	165576	0	0	0
T2	564752	57	0	0
T3	0	13	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	7	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	1	0	0
T82	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	3998	0	0
T1	165576	0	0	0
T2	564752	57	0	0
T3	0	13	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	7	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	1	0	0
T82	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Covered	T25,T2,T21
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504615272	4026	0	0
CgEnOn_A	504615272	4025	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	4026	0	0
T1	165576	0	0	0
T2	564752	51	0	0
T3	0	9	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	9	0	0
T23	0	8	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	4025	0	0
T1	165576	0	0	0
T2	564752	51	0	0
T3	0	9	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	9	0	0
T23	0	8	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T5
1	0	Covered	T25,T2,T21
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504615272	3991	0	0
CgEnOn_A	504615272	3990	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	3991	0	0
T1	165576	0	0	0
T2	564752	59	0	0
T3	0	9	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	7	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504615272	3990	0	0
T1	165576	0	0	0
T2	564752	59	0	0
T3	0	9	0	0
T4	69716	0	0	0
T5	50764	0	0	0
T17	4250	0	0	0
T18	2571	0	0	0
T19	1772	1	0	0
T20	4083	0	0	0
T21	0	8	0	0
T23	0	7	0	0
T25	2140	1	0	0
T26	15355	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T81	0	3	0	0
T82	0	9	0	0