Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616754	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3629480

1

T8

7

T6

10

T9

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1044408	1			T6	1		T9	20		T25	17
values[0x0]	1470686	1			T8	15		T6	12		T9	19
values[0x1]	1731140	1			T8	12		T6	10		T9	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	337170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3909064

1

T8

9

T6

15

T9

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15727	1			T5	8		T2	76		T18	1
valid_sources[0x01]	15235	1			T5	1		T2	76		T18	1
valid_sources[0x02]	16471	1			T5	6		T2	52		T3	193
valid_sources[0x03]	16874	1			T7	4		T1	3		T2	267
valid_sources[0x04]	17258	1			T7	2		T5	8		T2	52
valid_sources[0x05]	15945	1			T5	12		T1	3		T2	65
valid_sources[0x06]	17377	1			T6	1		T5	9		T2	102
valid_sources[0x07]	17998	1			T25	2		T2	113		T3	218
valid_sources[0x08]	16987	1			T7	8		T5	2		T2	22
valid_sources[0x09]	16785	1			T2	56		T3	242		T21	1
valid_sources[0x0a]	16788	1			T7	5		T5	6		T1	6
valid_sources[0x0b]	16540	1			T5	6		T2	91		T3	236
valid_sources[0x0c]	16696	1			T7	4		T5	4		T2	98
valid_sources[0x0d]	17402	1			T5	4		T2	64		T3	231
valid_sources[0x0e]	16280	1			T5	2		T33	7		T2	33
valid_sources[0x0f]	15996	1			T5	9		T2	151		T3	190
valid_sources[0x10]	16651	1			T7	9		T5	2		T1	1
valid_sources[0x11]	17845	1			T7	5		T5	7		T2	30
valid_sources[0x12]	16381	1			T7	6		T5	13		T33	3
valid_sources[0x13]	15602	1			T25	3		T7	1		T2	51
valid_sources[0x14]	16049	1			T7	1		T1	4		T2	108
valid_sources[0x15]	17131	1			T7	3		T5	4		T2	140
valid_sources[0x16]	17672	1			T9	61		T5	7		T2	39
valid_sources[0x17]	16520	1			T6	1		T7	5		T2	56
valid_sources[0x18]	16563	1			T5	3		T2	131		T3	203
valid_sources[0x19]	16546	1			T5	2		T2	86		T3	263
valid_sources[0x1a]	17608	1			T5	4		T2	62		T3	262
valid_sources[0x1b]	17771	1			T7	1		T5	8		T2	145
valid_sources[0x1c]	16357	1			T7	2		T1	2		T2	46
valid_sources[0x1d]	17293	1			T5	2		T2	125		T19	61
valid_sources[0x1e]	17149	1			T7	2		T5	1		T2	156
valid_sources[0x1f]	18175	1			T2	80		T3	254		T11	4
valid_sources[0x20]	16391	1			T5	2		T2	79		T3	221
valid_sources[0x21]	16049	1			T5	5		T2	65		T3	239
valid_sources[0x22]	16946	1			T1	3		T2	116		T18	3
valid_sources[0x23]	16855	1			T7	1		T5	3		T2	16
valid_sources[0x24]	16237	1			T5	1		T2	158		T3	231
valid_sources[0x25]	15961	1			T5	1		T1	3		T2	141
valid_sources[0x26]	15444	1			T7	3		T5	5		T2	54
valid_sources[0x27]	17030	1			T7	3		T2	29		T3	245
valid_sources[0x28]	16586	1			T5	2		T2	89		T18	1
valid_sources[0x29]	16292	1			T25	2		T5	3		T2	84
valid_sources[0x2a]	16213	1			T2	78		T3	277		T106	1
valid_sources[0x2b]	17247	1			T7	1		T2	38		T3	242
valid_sources[0x2c]	17336	1			T2	145		T3	214		T21	1
valid_sources[0x2d]	16293	1			T5	8		T2	71		T3	246
valid_sources[0x2e]	16931	1			T5	3		T1	9		T2	114
valid_sources[0x2f]	17220	1			T7	2		T5	4		T1	1
valid_sources[0x30]	16213	1			T6	1		T7	3		T5	2
valid_sources[0x31]	16035	1			T2	125		T3	227		T11	6
valid_sources[0x32]	16678	1			T5	5		T33	4		T2	28
valid_sources[0x33]	15458	1			T5	1		T2	128		T3	237
valid_sources[0x34]	16814	1			T25	1		T7	5		T5	8
valid_sources[0x35]	16400	1			T7	2		T5	2		T2	137
valid_sources[0x36]	15851	1			T25	2		T5	5		T2	51
valid_sources[0x37]	17538	1			T7	5		T5	10		T2	39
valid_sources[0x38]	16859	1			T7	3		T5	6		T2	52
valid_sources[0x39]	17363	1			T1	4		T2	61		T3	269
valid_sources[0x3a]	15470	1			T7	15		T5	5		T2	118
valid_sources[0x3b]	15426	1			T7	2		T5	6		T2	125
valid_sources[0x3c]	16971	1			T2	68		T3	234		T21	1
valid_sources[0x3d]	15190	1			T25	1		T7	2		T5	6
valid_sources[0x3e]	17031	1			T5	10		T1	2		T2	83
valid_sources[0x3f]	16920	1			T5	5		T2	25		T3	265
valid_sources[0x40]	17016	1			T5	4		T2	128		T3	246
valid_sources[0x41]	15393	1			T7	3		T5	3		T2	131
valid_sources[0x42]	16693	1			T7	5		T2	190		T3	254
valid_sources[0x43]	16889	1			T7	3		T5	9		T2	46
valid_sources[0x44]	16560	1			T7	3		T5	6		T2	152
valid_sources[0x45]	16320	1			T7	3		T5	5		T27	49
valid_sources[0x46]	17523	1			T5	8		T1	2		T2	51
valid_sources[0x47]	17275	1			T7	5		T5	8		T2	48
valid_sources[0x48]	16108	1			T7	8		T5	14		T2	90
valid_sources[0x49]	17142	1			T7	7		T2	102		T3	246
valid_sources[0x4a]	17447	1			T5	9		T1	3		T2	202
valid_sources[0x4b]	16505	1			T1	1		T2	111		T3	248
valid_sources[0x4c]	15948	1			T6	1		T7	3		T5	13
valid_sources[0x4d]	15938	1			T7	1		T2	88		T18	4
valid_sources[0x4e]	16019	1			T7	11		T5	1		T2	100
valid_sources[0x4f]	15537	1			T25	3		T7	2		T2	56
valid_sources[0x50]	16023	1			T7	3		T2	85		T3	271
valid_sources[0x51]	16386	1			T7	4		T5	4		T2	171
valid_sources[0x52]	17130	1			T5	4		T1	3		T2	80
valid_sources[0x53]	15941	1			T7	3		T5	1		T2	82
valid_sources[0x54]	16781	1			T25	2		T7	1		T5	2
valid_sources[0x55]	16605	1			T7	2		T5	13		T2	209
valid_sources[0x56]	15699	1			T2	74		T18	3		T3	257
valid_sources[0x57]	16910	1			T2	59		T3	203		T110	1
valid_sources[0x58]	16280	1			T2	162		T3	251		T11	5
valid_sources[0x59]	16247	1			T1	9		T2	93		T18	1
valid_sources[0x5a]	17195	1			T5	5		T1	2		T2	96
valid_sources[0x5b]	16449	1			T1	1		T2	61		T3	230
valid_sources[0x5c]	15425	1			T25	1		T2	25		T18	1
valid_sources[0x5d]	15986	1			T1	5		T2	77		T3	183
valid_sources[0x5e]	16771	1			T2	131		T3	268		T21	2
valid_sources[0x5f]	16848	1			T5	4		T2	127		T3	222
valid_sources[0x60]	16526	1			T5	4		T2	53		T3	230
valid_sources[0x61]	16879	1			T5	16		T1	4		T2	18
valid_sources[0x62]	18021	1			T7	2		T2	59		T18	3
valid_sources[0x63]	15739	1			T7	1		T2	75		T3	226
valid_sources[0x64]	17133	1			T7	5		T5	7		T2	69
valid_sources[0x65]	17129	1			T26	55		T2	109		T3	240
valid_sources[0x66]	15923	1			T7	3		T5	7		T2	95
valid_sources[0x67]	15876	1			T25	1		T7	1		T1	1
valid_sources[0x68]	17088	1			T4	705		T7	4		T5	2
valid_sources[0x69]	16153	1			T5	11		T33	12		T2	187
valid_sources[0x6a]	16742	1			T25	2		T7	4		T2	69
valid_sources[0x6b]	16232	1			T7	2		T5	3		T2	136
valid_sources[0x6c]	16530	1			T7	5		T1	1		T2	68
valid_sources[0x6d]	17628	1			T7	2		T2	122		T3	249
valid_sources[0x6e]	16775	1			T5	24		T1	2		T2	21
valid_sources[0x6f]	15163	1			T7	3		T5	14		T2	101
valid_sources[0x70]	16795	1			T25	2		T5	9		T1	1
valid_sources[0x71]	16031	1			T2	139		T18	2		T3	310
valid_sources[0x72]	17938	1			T2	51		T18	3		T3	192
valid_sources[0x73]	16565	1			T7	5		T5	1		T1	2
valid_sources[0x74]	16483	1			T7	2		T1	4		T2	25
valid_sources[0x75]	16085	1			T2	34		T3	269		T11	7
valid_sources[0x76]	16906	1			T2	88		T18	4		T3	260
valid_sources[0x77]	16533	1			T2	71		T3	217		T24	6
valid_sources[0x78]	15899	1			T7	2		T5	1		T2	65
valid_sources[0x79]	15883	1			T2	88		T3	198		T110	2
valid_sources[0x7a]	16585	1			T7	8		T2	47		T18	2
valid_sources[0x7b]	17107	1			T7	1		T5	17		T2	55
valid_sources[0x7c]	16616	1			T7	1		T5	6		T2	124
valid_sources[0x7d]	16635	1			T2	45		T3	253		T11	6
valid_sources[0x7e]	17438	1			T7	11		T5	1		T1	2
valid_sources[0x7f]	16030	1			T2	34		T3	232		T11	6
valid_sources[0x80]	16727	1			T7	2		T5	3		T33	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

916821

1

T9

5

T25

9

T4

186

values[0x0]

all_enables

biggest_size

1379194

1

T8

3

T6

9

T9

7

values[0x1]

all_enables

biggest_size

1333465

1

T8

4

T6

1

T9

3