Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T5
0	1	Covered	T8,T2,T20
1	0	Covered	T8,T6,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T5
1	0	Covered	T28,T39,T40
1	1	Covered	T8,T6,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	832682573	13369	0	0
GateOpen_A	832682573	19436	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832682573	13369	0	0
T2	0	118	0	0
T3	0	194	0	0
T4	164980	0	0	0
T5	303087	0	0	0
T6	35535	0	0	0
T7	430719	0	0	0
T8	3953	26	0	0
T9	5496	0	0	0
T11	0	14	0	0
T20	0	9	0	0
T22	0	4	0	0
T23	0	4	0	0
T25	41161	0	0	0
T26	7544	0	0	0
T27	16316	0	0	0
T28	6695	8	0	0
T31	0	18	0	0
T111	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	832682573	19436	0	0
T2	0	130	0	0
T4	164980	64	0	0
T5	303087	84	0	0
T6	35535	4	0	0
T7	430719	0	0	0
T8	3953	30	0	0
T9	5496	0	0	0
T18	0	4	0	0
T25	41161	0	0	0
T26	7544	4	0	0
T27	16316	4	0	0
T28	6695	12	0	0
T33	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T5
0	1	Covered	T8,T2,T20
1	0	Covered	T8,T6,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T5
1	0	Covered	T28,T39,T40
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	91770240	3144	0	0
GateOpen_A	91770240	4659	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91770240	3144	0	0
T2	0	26	0	0
T3	0	45	0	0
T4	12163	0	0	0
T5	25106	0	0	0
T6	3931	0	0	0
T7	45275	0	0	0
T8	426	6	0	0
T9	643	0	0	0
T11	0	3	0	0
T20	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	4953	0	0	0
T26	895	0	0	0
T27	1791	0	0	0
T28	727	2	0	0
T31	0	4	0	0
T111	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91770240	4659	0	0
T2	0	29	0	0
T4	12163	16	0	0
T5	25106	21	0	0
T6	3931	1	0	0
T7	45275	0	0	0
T8	426	7	0	0
T9	643	0	0	0
T18	0	1	0	0
T25	4953	0	0	0
T26	895	1	0	0
T27	1791	1	0	0
T28	727	3	0	0
T33	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T5
0	1	Covered	T8,T2,T20
1	0	Covered	T8,T6,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T5
1	0	Covered	T28,T39,T40
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	183541288	3408	0	0
GateOpen_A	183541288	4923	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183541288	3408	0	0
T2	0	32	0	0
T3	0	50	0	0
T4	24328	0	0	0
T5	50216	0	0	0
T6	7861	0	0	0
T7	90550	0	0	0
T8	852	6	0	0
T9	1290	0	0	0
T11	0	5	0	0
T20	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	9907	0	0	0
T26	1794	0	0	0
T27	3581	0	0	0
T28	1453	2	0	0
T31	0	5	0	0
T111	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183541288	4923	0	0
T2	0	35	0	0
T4	24328	16	0	0
T5	50216	21	0	0
T6	7861	1	0	0
T7	90550	0	0	0
T8	852	7	0	0
T9	1290	0	0	0
T18	0	1	0	0
T25	9907	0	0	0
T26	1794	1	0	0
T27	3581	1	0	0
T28	1453	3	0	0
T33	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T5
0	1	Covered	T8,T2,T20
1	0	Covered	T8,T6,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T5
1	0	Covered	T28,T39,T40
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	368246746	3411	0	0
GateOpen_A	368246746	4930	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368246746	3411	0	0
T2	0	28	0	0
T3	0	50	0	0
T4	85658	0	0	0
T5	151841	0	0	0
T6	15828	0	0	0
T7	181233	0	0	0
T8	1783	7	0	0
T9	2375	0	0	0
T11	0	3	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	17534	0	0	0
T26	3237	0	0	0
T27	7296	0	0	0
T28	3011	2	0	0
T31	0	5	0	0
T111	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368246746	4930	0	0
T2	0	31	0	0
T4	85658	16	0	0
T5	151841	21	0	0
T6	15828	1	0	0
T7	181233	0	0	0
T8	1783	8	0	0
T9	2375	0	0	0
T18	0	1	0	0
T25	17534	0	0	0
T26	3237	1	0	0
T27	7296	1	0	0
T28	3011	3	0	0
T33	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T4,T5
0	1	Covered	T8,T2,T20
1	0	Covered	T8,T6,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T5
1	0	Covered	T28,T39,T40
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	189124299	3406	0	0
GateOpen_A	189124299	4924	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189124299	3406	0	0
T2	0	32	0	0
T3	0	49	0	0
T4	42831	0	0	0
T5	75924	0	0	0
T6	7915	0	0	0
T7	113661	0	0	0
T8	892	7	0	0
T9	1188	0	0	0
T11	0	3	0	0
T20	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	8767	0	0	0
T26	1618	0	0	0
T27	3648	0	0	0
T28	1504	2	0	0
T31	0	4	0	0
T111	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189124299	4924	0	0
T2	0	35	0	0
T4	42831	16	0	0
T5	75924	21	0	0
T6	7915	1	0	0
T7	113661	0	0	0
T8	892	8	0	0
T9	1188	0	0	0
T18	0	1	0	0
T25	8767	0	0	0
T26	1618	1	0	0
T27	3648	1	0	0
T28	1504	3	0	0
T33	0	1	0	0