Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	783928595	80731	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783928595	80731	0	0
T1	140755	56	0	0
T2	2944315	448	0	0
T3	1206275	612	0	0
T11	0	248	0	0
T12	0	39	0	0
T13	0	183	0	0
T14	0	1024	0	0
T15	0	835	0	0
T16	0	149	0	0
T17	0	1540	0	0
T18	467785	0	0	0
T19	11480	0	0	0
T20	7315	0	0	0
T21	106410	0	0	0
T22	8650	0	0	0
T23	7575	0	0	0
T24	10715	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156785719	11694	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	11694	0	0
T1	28151	9	0	0
T2	588863	64	0	0
T3	241255	97	0	0
T11	0	40	0	0
T12	0	6	0	0
T13	0	35	0	0
T14	0	134	0	0
T15	0	106	0	0
T16	0	22	0	0
T17	0	220	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156785719	11498	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	11498	0	0
T1	28151	9	0	0
T2	588863	63	0	0
T3	241255	96	0	0
T11	0	40	0	0
T12	0	6	0	0
T13	0	35	0	0
T14	0	151	0	0
T15	0	120	0	0
T16	0	22	0	0
T17	0	219	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156785719	16252	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	16252	0	0
T1	28151	11	0	0
T2	588863	101	0	0
T3	241255	122	0	0
T11	0	50	0	0
T12	0	8	0	0
T13	0	35	0	0
T14	0	201	0	0
T15	0	161	0	0
T16	0	30	0	0
T17	0	310	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156785719	16230	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	16230	0	0
T1	28151	11	0	0
T2	588863	87	0	0
T3	241255	123	0	0
T11	0	50	0	0
T12	0	8	0	0
T13	0	35	0	0
T14	0	203	0	0
T15	0	169	0	0
T16	0	30	0	0
T17	0	312	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156785719	25057	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	25057	0	0
T1	28151	16	0	0
T2	588863	133	0	0
T3	241255	174	0	0
T11	0	68	0	0
T12	0	11	0	0
T13	0	43	0	0
T14	0	335	0	0
T15	0	279	0	0
T16	0	45	0	0
T17	0	479	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0