Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T4,T5,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	156785719	154339818	0	0
AllClkBypReqTrue_A	156785719	123079	0	0
IoClkBypReqFalse_A	156785719	154263507	0	2415
IoClkBypReqTrue_A	156785719	195014	0	0
LcClkBypAckFalse_A	156785719	154349545	0	0
LcClkBypAckTrue_A	156785719	113352	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	154339818	0	0
T4	89229	4574	0	0
T5	39542	9614	0	0
T6	3956	3898	0	0
T7	84977	84913	0	0
T8	1857	1672	0	0
T9	2473	2008	0	0
T25	1826	1631	0	0
T26	2562	2072	0	0
T27	1671	1630	0	0
T28	805	759	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	123079	0	0
T1	28151	0	0	0
T2	0	732	0	0
T3	0	1930	0	0
T4	89229	0	0	0
T5	39542	0	0	0
T7	84977	0	0	0
T9	2473	295	0	0
T11	0	205	0	0
T19	0	275	0	0
T25	1826	179	0	0
T26	2562	382	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0
T106	0	29	0	0
T107	0	4	0	0
T108	0	22	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	154263507	0	2415
T4	89229	4542	0	3
T5	39542	9572	0	3
T6	3956	3896	0	3
T7	84977	84911	0	3
T8	1857	1670	0	3
T9	2473	1877	0	3
T25	1826	1493	0	3
T26	2562	2003	0	3
T27	1671	1628	0	3
T28	805	757	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	195014	0	0
T1	28151	0	0	0
T2	0	1437	0	0
T3	0	2676	0	0
T4	89229	0	0	0
T5	39542	0	0	0
T7	84977	0	0	0
T9	2473	424	0	0
T11	0	417	0	0
T14	0	3590	0	0
T19	0	476	0	0
T25	1826	315	0	0
T26	2562	449	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0
T106	0	283	0	0
T109	0	355	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	154349545	0	0
T4	89229	4574	0	0
T5	39542	9614	0	0
T6	3956	3898	0	0
T7	84977	84913	0	0
T8	1857	1672	0	0
T9	2473	2097	0	0
T25	1826	1628	0	0
T26	2562	2170	0	0
T27	1671	1630	0	0
T28	805	759	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	113352	0	0
T1	28151	0	0	0
T2	0	935	0	0
T3	0	1388	0	0
T4	89229	0	0	0
T5	39542	0	0	0
T7	84977	0	0	0
T9	2473	206	0	0
T11	0	285	0	0
T14	0	2011	0	0
T19	0	267	0	0
T25	1826	182	0	0
T26	2562	284	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0
T106	0	115	0	0
T109	0	93	0	0