Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1575997716	15701	0	0
TransStop_A	1575997716	8082	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575997716	15701	0	0
T1	388308	0	0	0
T2	488308	232	0	0
T3	3072172	219	0	0
T11	0	10	0	0
T18	365840	0	0	0
T19	18744	0	0	0
T20	5972	0	0	0
T21	87756	0	0	0
T22	0	4	0	0
T23	0	4	0	0
T24	0	27	0	0
T27	30396	13	0	0
T28	12176	0	0	0
T33	12212	0	0	0
T110	0	16	0	0
T111	0	4	0	0
T112	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575997716	8082	0	0
T1	388308	0	0	0
T2	488308	129	0	0
T3	3072172	112	0	0
T11	0	6	0	0
T18	365840	0	0	0
T19	18744	0	0	0
T20	5972	0	0	0
T21	87756	0	0	0
T22	0	4	0	0
T23	0	4	0	0
T24	0	16	0	0
T27	30396	6	0	0
T28	12176	0	0	0
T33	12212	0	0	0
T110	0	8	0	0
T111	0	4	0	0
T112	0	4	0	0
T113	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	393999429	3957	0	0
TransStop_A	393999429	2060	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	3957	0	0
T1	97077	0	0	0
T2	122077	63	0	0
T3	768043	53	0	0
T11	0	2	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	4	0	0
T27	7599	2	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	2060	0	0
T1	97077	0	0	0
T2	122077	41	0	0
T3	768043	27	0	0
T11	0	1	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	3	0	0
T27	7599	1	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	393999429	3904	0	0
TransStop_A	393999429	1989	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	3904	0	0
T1	97077	0	0	0
T2	122077	55	0	0
T3	768043	60	0	0
T11	0	2	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	10	0	0
T27	7599	4	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	5	0	0
T111	0	1	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	1989	0	0
T1	97077	0	0	0
T2	122077	28	0	0
T3	768043	31	0	0
T11	0	1	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	4	0	0
T27	7599	2	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	393999429	3913	0	0
TransStop_A	393999429	2018	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	3913	0	0
T1	97077	0	0	0
T2	122077	62	0	0
T3	768043	54	0	0
T11	0	3	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	8	0	0
T27	7599	3	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	5	0	0
T111	0	1	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	2018	0	0
T1	97077	0	0	0
T2	122077	32	0	0
T3	768043	28	0	0
T11	0	2	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	6	0	0
T27	7599	2	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	393999429	3927	0	0
TransStop_A	393999429	2015	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	3927	0	0
T1	97077	0	0	0
T2	122077	52	0	0
T3	768043	52	0	0
T11	0	3	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	7599	4	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393999429	2015	0	0
T1	97077	0	0	0
T2	122077	28	0	0
T3	768043	26	0	0
T11	0	2	0	0
T18	91460	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	3	0	0
T27	7599	1	0	0
T28	3044	0	0	0
T33	3053	0	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	9	0	0