Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T6,T9
01CoveredT8,T6,T9
10CoveredT9,T25,T26 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T6,T9
10CoveredT9,T25,T26
11CoveredT9,T25,T26 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T25,T26
10CoveredT8,T6,T9
11CoveredT8,T6,T9
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 458484586 458482171 0 0
selKnown1 1104738939 1104736524 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 458484586 458482171 0 0
T4 60819 60816 0 0
T5 125537 125534 0 0
T6 19650 19647 0 0
T7 226373 226370 0 0
T8 2130 2127 0 0
T9 3058 3055 0 0
T25 23592 23589 0 0
T26 4254 4251 0 0
T27 8950 8947 0 0
T28 3630 3627 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1104738939 1104736524 0 0
T4 256971 256968 0 0
T5 455523 455520 0 0
T6 47481 47478 0 0
T7 543696 543693 0 0
T8 5346 5343 0 0
T9 7125 7122 0 0
T25 52602 52599 0 0
T26 9708 9705 0 0
T27 21885 21882 0 0
T28 9033 9030 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T6,T9
01CoveredT8,T6,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T6,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T6,T9
11CoveredT8,T6,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 183540877 183540072 0 0
selKnown1 368246313 368245508 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 183540877 183540072 0 0
T4 24328 24327 0 0
T5 50216 50215 0 0
T6 7860 7859 0 0
T7 90549 90548 0 0
T8 852 851 0 0
T9 1289 1288 0 0
T25 9906 9905 0 0
T26 1794 1793 0 0
T27 3580 3579 0 0
T28 1452 1451 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246313 368245508 0 0
T4 85657 85656 0 0
T5 151841 151840 0 0
T6 15827 15826 0 0
T7 181232 181231 0 0
T8 1782 1781 0 0
T9 2375 2374 0 0
T25 17534 17533 0 0
T26 3236 3235 0 0
T27 7295 7294 0 0
T28 3011 3010 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T6,T9
01CoveredT8,T6,T9
10CoveredT9,T25,T26 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T6,T9
10CoveredT9,T25,T26
11CoveredT9,T25,T26 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T25,T26
10CoveredT8,T6,T9
11CoveredT8,T6,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 183173877 183173072 0 0
selKnown1 368246313 368245508 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 183173877 183173072 0 0
T4 24328 24327 0 0
T5 50216 50215 0 0
T6 7860 7859 0 0
T7 90549 90548 0 0
T8 852 851 0 0
T9 1127 1126 0 0
T25 8734 8733 0 0
T26 1565 1564 0 0
T27 3580 3579 0 0
T28 1452 1451 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246313 368245508 0 0
T4 85657 85656 0 0
T5 151841 151840 0 0
T6 15827 15826 0 0
T7 181232 181231 0 0
T8 1782 1781 0 0
T9 2375 2374 0 0
T25 17534 17533 0 0
T26 3236 3235 0 0
T27 7295 7294 0 0
T28 3011 3010 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T6,T9
01CoveredT8,T6,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T6,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T6,T9
11CoveredT8,T6,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 91769832 91769027 0 0
selKnown1 368246313 368245508 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 91769832 91769027 0 0
T4 12163 12162 0 0
T5 25105 25104 0 0
T6 3930 3929 0 0
T7 45275 45274 0 0
T8 426 425 0 0
T9 642 641 0 0
T25 4952 4951 0 0
T26 895 894 0 0
T27 1790 1789 0 0
T28 726 725 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246313 368245508 0 0
T4 85657 85656 0 0
T5 151841 151840 0 0
T6 15827 15826 0 0
T7 181232 181231 0 0
T8 1782 1781 0 0
T9 2375 2374 0 0
T25 17534 17533 0 0
T26 3236 3235 0 0
T27 7295 7294 0 0
T28 3011 3010 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%