Module Definition
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Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_byp_req

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_byp_req

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 1157345 63288 0 0
T5 1724038 444289 0 0
T6 153712 151161 0 0
T7 2519649 2517754 0 0
T8 25467 23093 0 0
T9 34527 32438 0 0
T25 207296 205711 0 0
T26 44794 43167 0 0
T27 86811 84983 0 0
T28 35517 33618 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 156785719 154465085 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156785719 154465085 0 0
T4 89229 4590 0 0
T5 39542 9635 0 0
T6 3956 3899 0 0
T7 84977 84914 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 1826 1811 0 0
T26 2562 2455 0 0
T27 1671 1631 0 0
T28 805 760 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 156785719 154465085 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156785719 154465085 0 0
T4 89229 4590 0 0
T5 39542 9635 0 0
T6 3956 3899 0 0
T7 84977 84914 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 1826 1811 0 0
T26 2562 2455 0 0
T27 1671 1631 0 0
T28 805 760 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 156785719 154465085 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 156785719 154465085 0 0
T4 89229 4590 0 0
T5 39542 9635 0 0
T6 3956 3899 0 0
T7 84977 84914 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 1826 1811 0 0
T26 2562 2455 0 0
T27 1671 1631 0 0
T28 805 760 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 91769832 91301106 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91769832 91301106 0 0
T4 12163 1099 0 0
T5 25105 9231 0 0
T6 3930 3899 0 0
T7 45275 45265 0 0
T8 426 402 0 0
T9 642 632 0 0
T25 4952 4931 0 0
T26 895 888 0 0
T27 1790 1780 0 0
T28 726 709 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 393998983 389937318 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393998983 389937318 0 0
T4 89229 4590 0 0
T5 158172 38460 0 0
T6 10487 10247 0 0
T7 218789 218606 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 18266 18111 0 0
T26 3372 3231 0 0
T27 7599 7416 0 0
T28 3044 2861 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 189123907 187180486 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189123907 187180486 0 0
T4 42831 2197 0 0
T5 75923 18462 0 0
T6 7914 7799 0 0
T7 113661 113573 0 0
T8 891 803 0 0
T9 1187 1106 0 0
T25 8767 8693 0 0
T26 1618 1551 0 0
T27 3647 3559 0 0
T28 1504 1416 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 368246313 364472341 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246313 364472341 0 0
T4 85657 4394 0 0
T5 151841 36921 0 0
T6 15827 15596 0 0
T7 181232 181057 0 0
T8 1782 1607 0 0
T9 2375 2213 0 0
T25 17534 17386 0 0
T26 3236 3101 0 0
T27 7295 7119 0 0
T28 3011 2835 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 183540877 182603263 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 183540877 182603263 0 0
T4 24328 2200 0 0
T5 50216 18467 0 0
T6 7860 7798 0 0
T7 90549 90528 0 0
T8 852 804 0 0
T9 1289 1268 0 0
T25 9906 9865 0 0
T26 1794 1780 0 0
T27 3580 3559 0 0
T28 1452 1417 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 91769832 91301106 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91769832 91301106 0 0
T4 12163 1099 0 0
T5 25105 9231 0 0
T6 3930 3899 0 0
T7 45275 45265 0 0
T8 426 402 0 0
T9 642 632 0 0
T25 4952 4931 0 0
T26 895 888 0 0
T27 1790 1780 0 0
T28 726 709 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 393998983 389937318 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393998983 389937318 0 0
T4 89229 4590 0 0
T5 158172 38460 0 0
T6 10487 10247 0 0
T7 218789 218606 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 18266 18111 0 0
T26 3372 3231 0 0
T27 7599 7416 0 0
T28 3044 2861 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 91769832 91301106 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91769832 91301106 0 0
T4 12163 1099 0 0
T5 25105 9231 0 0
T6 3930 3899 0 0
T7 45275 45265 0 0
T8 426 402 0 0
T9 642 632 0 0
T25 4952 4931 0 0
T26 895 888 0 0
T27 1790 1780 0 0
T28 726 709 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 91769832 91301106 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91769832 91301106 0 0
T4 12163 1099 0 0
T5 25105 9231 0 0
T6 3930 3899 0 0
T7 45275 45265 0 0
T8 426 402 0 0
T9 642 632 0 0
T25 4952 4931 0 0
T26 895 888 0 0
T27 1790 1780 0 0
T28 726 709 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 183540877 182603263 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 183540877 182603263 0 0
T4 24328 2200 0 0
T5 50216 18467 0 0
T6 7860 7798 0 0
T7 90549 90528 0 0
T8 852 804 0 0
T9 1289 1268 0 0
T25 9906 9865 0 0
T26 1794 1780 0 0
T27 3580 3559 0 0
T28 1452 1417 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 368246313 364472341 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246313 364472341 0 0
T4 85657 4394 0 0
T5 151841 36921 0 0
T6 15827 15596 0 0
T7 181232 181057 0 0
T8 1782 1607 0 0
T9 2375 2213 0 0
T25 17534 17386 0 0
T26 3236 3101 0 0
T27 7295 7119 0 0
T28 3011 2835 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 189123907 187180486 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 189123907 187180486 0 0
T4 42831 2197 0 0
T5 75923 18462 0 0
T6 7914 7799 0 0
T7 113661 113573 0 0
T8 891 803 0 0
T9 1187 1106 0 0
T25 8767 8693 0 0
T26 1618 1551 0 0
T27 3647 3559 0 0
T28 1504 1416 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 393998983 389937318 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393998983 389937318 0 0
T4 89229 4590 0 0
T5 158172 38460 0 0
T6 10487 10247 0 0
T7 218789 218606 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 18266 18111 0 0
T26 3372 3231 0 0
T27 7599 7416 0 0
T28 3044 2861 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 393998983 389937318 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393998983 389937318 0 0
T4 89229 4590 0 0
T5 158172 38460 0 0
T6 10487 10247 0 0
T7 218789 218606 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 18266 18111 0 0
T26 3372 3231 0 0
T27 7599 7416 0 0
T28 3044 2861 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 393998983 389937318 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393998983 389937318 0 0
T4 89229 4590 0 0
T5 158172 38460 0 0
T6 10487 10247 0 0
T7 218789 218606 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 18266 18111 0 0
T26 3372 3231 0 0
T27 7599 7416 0 0
T28 3044 2861 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 393998983 389937318 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393998983 389937318 0 0
T4 89229 4590 0 0
T5 158172 38460 0 0
T6 10487 10247 0 0
T7 218789 218606 0 0
T8 1857 1673 0 0
T9 2473 2304 0 0
T25 18266 18111 0 0
T26 3372 3231 0 0
T27 7599 7416 0 0
T28 3044 2861 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%