Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	156785719	19993944	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	19993944	0	60
T1	28151	4607	0	1
T2	588863	42468	0	0
T3	241255	651070	0	0
T11	0	15573	0	0
T12	0	4086	0	1
T13	0	5829	0	1
T14	0	213364	0	0
T15	0	99156	0	1
T16	0	12626	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0
T29	0	541	0	0
T114	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1