Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	157802665	5324569	0	0
clk_enables_rd_A	157802665	25830	0	0
clk_hints_rd_A	157802665	22425	0	0
extclk_ctrl_rd_A	157802665	27318	0	0
extclk_ctrl_regwen_rd_A	157802665	21181	0	0
jitter_enable_rd_A	157802665	31872	0	0
jitter_regwen_rd_A	157802665	22688	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	5324569	0	0
T2	588863	29140	0	0
T3	241255	81611	0	0
T14	0	105811	0	0
T17	0	213072	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T23	1515	0	0	0
T24	2143	0	0	0
T31	1028	0	0	0
T65	0	29193	0	0
T66	0	150257	0	0
T67	0	46621	0	0
T68	0	93974	0	0
T69	0	149733	0	0
T70	0	72293	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	25830	0	0
T12	36329	0	0	0
T13	21026	0	0	0
T14	0	2292	0	0
T16	0	26	0	0
T30	0	16	0	0
T32	25523	0	0	0
T35	901	0	0	0
T66	0	5771	0	0
T71	25173	0	0	0
T72	23695	0	0	0
T109	2207	0	0	0
T112	1996	9	0	0
T113	2841	0	0	0
T136	0	5	0	0
T137	0	2	0	0
T138	0	10	0	0
T139	0	2	0	0
T140	0	4584	0	0
T141	1484	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	22425	0	0
T12	36329	0	0	0
T13	21026	0	0	0
T14	0	2133	0	0
T16	0	15	0	0
T30	0	11	0	0
T32	25523	0	0	0
T35	901	0	0	0
T66	0	4869	0	0
T71	25173	0	0	0
T72	23695	0	0	0
T109	2207	0	0	0
T112	1996	1	0	0
T113	2841	0	0	0
T136	0	9	0	0
T137	0	2	0	0
T141	1484	0	0	0
T142	0	3	0	0
T143	0	4	0	0
T144	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	27318	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T5	39542	87	0	0
T14	0	2345	0	0
T16	0	81	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	0	27	0	0
T26	2562	51	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0
T51	0	36	0	0
T80	0	58	0	0
T87	0	78	0	0
T88	0	42	0	0
T145	0	83	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	21181	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T5	39542	54	0	0
T14	0	1968	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	0	11	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0
T38	0	482	0	0
T66	0	4847	0	0
T140	0	3910	0	0
T145	0	42	0	0
T146	0	42	0	0
T147	0	23	0	0
T148	0	10	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	31872	0	0
T12	36329	0	0	0
T13	21026	0	0	0
T14	0	2814	0	0
T16	0	670	0	0
T30	0	335	0	0
T32	25523	0	0	0
T35	901	0	0	0
T66	0	6515	0	0
T71	25173	0	0	0
T72	23695	0	0	0
T109	2207	0	0	0
T112	1996	102	0	0
T113	2841	0	0	0
T136	0	419	0	0
T137	0	102	0	0
T141	1484	0	0	0
T142	0	105	0	0
T143	0	58	0	0
T144	0	69	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	22688	0	0
T14	334816	2145	0	0
T29	14670	0	0	0
T38	0	523	0	0
T39	1310	0	0	0
T40	942	0	0	0
T55	0	59	0	0
T57	0	103	0	0
T66	0	5784	0	0
T74	0	49	0	0
T95	0	83	0	0
T140	0	4032	0	0
T145	114634	0	0	0
T149	0	2039	0	0
T150	0	5890	0	0
T151	2145	0	0	0
T152	1523	0	0	0
T153	1208	0	0	0
T154	2713	0	0	0
T155	1037	0	0	0