Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T25
10CoveredT9,T25,T26
11CoveredT9,T25,T26

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 368246746 4250 0 0
g_div2.Div2Whole_A 368246746 5085 0 0
g_div4.Div4Stepped_A 183541288 4150 0 0
g_div4.Div4Whole_A 183541288 4813 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246746 4250 0 0
T1 93191 0 0 0
T2 0 34 0 0
T3 0 55 0 0
T4 85658 0 0 0
T5 151841 0 0 0
T7 181233 0 0 0
T9 2375 6 0 0
T11 0 10 0 0
T19 0 10 0 0
T25 17534 12 0 0
T26 3237 12 0 0
T27 7296 0 0 0
T28 3011 0 0 0
T33 2931 0 0 0
T106 0 4 0 0
T107 0 1 0 0
T108 0 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246746 5085 0 0
T1 93191 0 0 0
T2 0 44 0 0
T3 0 59 0 0
T4 85658 0 0 0
T5 151841 0 0 0
T7 181233 0 0 0
T9 2375 14 0 0
T11 0 11 0 0
T19 0 12 0 0
T25 17534 12 0 0
T26 3237 13 0 0
T27 7296 0 0 0
T28 3011 0 0 0
T33 2931 0 0 0
T106 0 8 0 0
T107 0 1 0 0
T108 0 3 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 183541288 4150 0 0
T1 46556 0 0 0
T2 0 33 0 0
T3 0 54 0 0
T4 24328 0 0 0
T5 50216 0 0 0
T7 90550 0 0 0
T9 1290 6 0 0
T11 0 10 0 0
T19 0 10 0 0
T25 9907 12 0 0
T26 1794 10 0 0
T27 3581 0 0 0
T28 1453 0 0 0
T33 1453 0 0 0
T106 0 3 0 0
T107 0 1 0 0
T108 0 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 183541288 4813 0 0
T1 46556 0 0 0
T2 0 44 0 0
T3 0 59 0 0
T4 24328 0 0 0
T5 50216 0 0 0
T7 90550 0 0 0
T9 1290 14 0 0
T11 0 11 0 0
T19 0 12 0 0
T25 9907 11 0 0
T26 1794 12 0 0
T27 3581 0 0 0
T28 1453 0 0 0
T33 1453 0 0 0
T106 0 8 0 0
T107 0 1 0 0
T108 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T25
10CoveredT9,T25,T26
11CoveredT9,T25,T26

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 368246746 4250 0 0
g_div2.Div2Whole_A 368246746 5085 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246746 4250 0 0
T1 93191 0 0 0
T2 0 34 0 0
T3 0 55 0 0
T4 85658 0 0 0
T5 151841 0 0 0
T7 181233 0 0 0
T9 2375 6 0 0
T11 0 10 0 0
T19 0 10 0 0
T25 17534 12 0 0
T26 3237 12 0 0
T27 7296 0 0 0
T28 3011 0 0 0
T33 2931 0 0 0
T106 0 4 0 0
T107 0 1 0 0
T108 0 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 368246746 5085 0 0
T1 93191 0 0 0
T2 0 44 0 0
T3 0 59 0 0
T4 85658 0 0 0
T5 151841 0 0 0
T7 181233 0 0 0
T9 2375 14 0 0
T11 0 11 0 0
T19 0 12 0 0
T25 17534 12 0 0
T26 3237 13 0 0
T27 7296 0 0 0
T28 3011 0 0 0
T33 2931 0 0 0
T106 0 8 0 0
T107 0 1 0 0
T108 0 3 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T25
10CoveredT9,T25,T26
11CoveredT9,T25,T26

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 183541288 4150 0 0
g_div4.Div4Whole_A 183541288 4813 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 183541288 4150 0 0
T1 46556 0 0 0
T2 0 33 0 0
T3 0 54 0 0
T4 24328 0 0 0
T5 50216 0 0 0
T7 90550 0 0 0
T9 1290 6 0 0
T11 0 10 0 0
T19 0 10 0 0
T25 9907 12 0 0
T26 1794 10 0 0
T27 3581 0 0 0
T28 1453 0 0 0
T33 1453 0 0 0
T106 0 3 0 0
T107 0 1 0 0
T108 0 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 183541288 4813 0 0
T1 46556 0 0 0
T2 0 44 0 0
T3 0 59 0 0
T4 24328 0 0 0
T5 50216 0 0 0
T7 90550 0 0 0
T9 1290 14 0 0
T11 0 11 0 0
T19 0 12 0 0
T25 9907 11 0 0
T26 1794 12 0 0
T27 3581 0 0 0
T28 1453 0 0 0
T33 1453 0 0 0
T106 0 8 0 0
T107 0 1 0 0
T108 0 2 0 0

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