Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	470357157	457	0	0
StatusRise_A	470357157	457	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470357157	457	0	0
T1	84453	0	0	0
T2	1766589	0	0	0
T3	723765	0	0	0
T18	280671	0	0	0
T19	6888	0	0	0
T20	4389	0	0	0
T21	63846	0	0	0
T22	5190	0	0	0
T28	2415	6	0	0
T33	4395	0	0	0
T39	0	3	0	0
T40	0	8	0	0
T79	0	8	0	0
T156	0	10	0	0
T157	0	7	0	0
T158	0	16	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	11	0	0
T162	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470357157	457	0	0
T1	84453	0	0	0
T2	1766589	0	0	0
T3	723765	0	0	0
T18	280671	0	0	0
T19	6888	0	0	0
T20	4389	0	0	0
T21	63846	0	0	0
T22	5190	0	0	0
T28	2415	6	0	0
T33	4395	0	0	0
T39	0	3	0	0
T40	0	8	0	0
T79	0	8	0	0
T156	0	10	0	0
T157	0	7	0	0
T158	0	16	0	0
T159	0	4	0	0
T160	0	6	0	0
T161	0	11	0	0
T162	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156785719	168	0	0
StatusRise_A	156785719	168	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	168	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T28	805	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	5	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	168	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T28	805	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	5	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156785719	149	0	0
StatusRise_A	156785719	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	149	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T28	805	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0
T161	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	149	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T28	805	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0
T161	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156785719	140	0	0
StatusRise_A	156785719	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	140	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T28	805	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	5	0	0
T160	0	2	0	0
T161	0	4	0	0
T162	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156785719	140	0	0
T1	28151	0	0	0
T2	588863	0	0	0
T3	241255	0	0	0
T18	93557	0	0	0
T19	2296	0	0	0
T20	1463	0	0	0
T21	21282	0	0	0
T22	1730	0	0	0
T28	805	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	5	0	0
T160	0	2	0	0
T161	0	4	0	0
T162	0	1	0	0