Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Covered	T8,T6,T9
1	1	Covered	T8,T6,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47275	0	0
CgEnOn_A	2147483647	38529	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47275	0	0
T1	838641	0	0	0
T2	2848212	63	0	0
T3	6619660	53	0	0
T4	164979	48	0	0
T5	303085	63	0	0
T6	35531	3	0	0
T7	430717	3	0	0
T8	3951	32	0	0
T9	5493	3	0	0
T17	0	5	0	0
T18	755487	0	0	0
T19	41149	0	0	0
T20	12851	0	0	0
T21	175606	0	0	0
T22	7895	0	0	0
T25	41159	3	0	0
T26	7543	3	0	0
T27	46708	5	0	0
T28	33102	21	0	0
T33	26338	0	0	0
T39	0	5	0	0
T40	0	10	0	0
T79	0	10	0	0
T156	0	15	0	0
T157	0	15	0	0
T158	0	30	0	0
T159	0	10	0	0
T160	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38529	0	0
T1	838641	0	0	0
T2	2848212	213	0	0
T3	6619660	286	0	0
T4	164979	0	0	0
T5	303085	0	0	0
T6	35531	0	0	0
T7	430717	0	0	0
T8	3951	29	0	0
T9	5493	0	0	0
T11	0	33	0	0
T17	0	4	0	0
T18	755487	0	0	0
T19	41149	0	0	0
T20	12851	18	0	0
T21	175606	0	0	0
T22	7895	4	0	0
T23	0	4	0	0
T25	41159	0	0	0
T26	7543	0	0	0
T27	46708	2	0	0
T28	33102	18	0	0
T31	0	27	0	0
T33	26338	0	0	0
T39	0	5	0	0
T40	0	10	0	0
T79	0	10	0	0
T111	0	4	0	0
T156	0	15	0	0
T157	0	15	0	0
T158	0	30	0	0
T159	0	10	0	0
T160	0	15	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	183540877	163	0	0
CgEnOn_A	183540877	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183540877	163	0	0
T1	46556	0	0	0
T2	568423	0	0	0
T3	364250	0	0	0
T17	0	1	0	0
T18	38078	0	0	0
T19	2515	0	0	0
T20	697	0	0	0
T21	4952	0	0	0
T22	777	0	0	0
T28	1452	2	0	0
T33	1453	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183540877	163	0	0
T1	46556	0	0	0
T2	568423	0	0	0
T3	364250	0	0	0
T17	0	1	0	0
T18	38078	0	0	0
T19	2515	0	0	0
T20	697	0	0	0
T21	4952	0	0	0
T22	777	0	0	0
T28	1452	2	0	0
T33	1453	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91769832	163	0	0
CgEnOn_A	91769832	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	163	0	0
T1	23278	0	0	0
T2	284206	0	0	0
T3	182124	0	0	0
T17	0	1	0	0
T18	19039	0	0	0
T19	1257	0	0	0
T20	349	0	0	0
T21	2476	0	0	0
T22	389	0	0	0
T28	726	2	0	0
T33	726	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	163	0	0
T1	23278	0	0	0
T2	284206	0	0	0
T3	182124	0	0	0
T17	0	1	0	0
T18	19039	0	0	0
T19	1257	0	0	0
T20	349	0	0	0
T21	2476	0	0	0
T22	389	0	0	0
T28	726	2	0	0
T33	726	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91769832	163	0	0
CgEnOn_A	91769832	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	163	0	0
T1	23278	0	0	0
T2	284206	0	0	0
T3	182124	0	0	0
T17	0	1	0	0
T18	19039	0	0	0
T19	1257	0	0	0
T20	349	0	0	0
T21	2476	0	0	0
T22	389	0	0	0
T28	726	2	0	0
T33	726	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	163	0	0
T1	23278	0	0	0
T2	284206	0	0	0
T3	182124	0	0	0
T17	0	1	0	0
T18	19039	0	0	0
T19	1257	0	0	0
T20	349	0	0	0
T21	2476	0	0	0
T22	389	0	0	0
T28	726	2	0	0
T33	726	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91769832	163	0	0
CgEnOn_A	91769832	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	163	0	0
T1	23278	0	0	0
T2	284206	0	0	0
T3	182124	0	0	0
T17	0	1	0	0
T18	19039	0	0	0
T19	1257	0	0	0
T20	349	0	0	0
T21	2476	0	0	0
T22	389	0	0	0
T28	726	2	0	0
T33	726	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	163	0	0
T1	23278	0	0	0
T2	284206	0	0	0
T3	182124	0	0	0
T17	0	1	0	0
T18	19039	0	0	0
T19	1257	0	0	0
T20	349	0	0	0
T21	2476	0	0	0
T22	389	0	0	0
T28	726	2	0	0
T33	726	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	368246313	163	0	0
CgEnOn_A	368246313	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368246313	163	0	0
T1	93191	0	0	0
T2	114486	0	0	0
T3	729234	0	0	0
T17	0	1	0	0
T18	76277	0	0	0
T19	4498	0	0	0
T20	1433	0	0	0
T21	21061	0	0	0
T22	1661	0	0	0
T28	3011	2	0	0
T33	2930	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368246313	151	0	0
T1	93191	0	0	0
T2	114486	0	0	0
T3	729234	0	0	0
T18	76277	0	0	0
T19	4498	0	0	0
T20	1433	0	0	0
T21	21061	0	0	0
T22	1661	0	0	0
T28	3011	2	0	0
T33	2930	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T79	0	2	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	3	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393998983	172	0	0
CgEnOn_A	393998983	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	172	0	0
T1	97077	0	0	0
T2	122077	0	0	0
T3	768043	0	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	1730	0	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	5	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	170	0	0
T1	97077	0	0	0
T2	122077	0	0	0
T3	768043	0	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	1730	0	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	5	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393998983	172	0	0
CgEnOn_A	393998983	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	172	0	0
T1	97077	0	0	0
T2	122077	0	0	0
T3	768043	0	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	1730	0	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	5	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	170	0	0
T1	97077	0	0	0
T2	122077	0	0	0
T3	768043	0	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	1730	0	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	5	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Unreachable
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	189123907	144	0	0
CgEnOn_A	189123907	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189123907	144	0	0
T1	46598	0	0	0
T2	580223	0	0	0
T3	371546	0	0	0
T14	0	1	0	0
T18	35261	0	0	0
T19	2249	0	0	0
T20	716	0	0	0
T21	10531	0	0	0
T22	830	0	0	0
T28	1504	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	5	0	0
T160	0	2	0	0
T161	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189123907	142	0	0
T1	46598	0	0	0
T2	580223	0	0	0
T3	371546	0	0	0
T14	0	1	0	0
T18	35261	0	0	0
T19	2249	0	0	0
T20	716	0	0	0
T21	10531	0	0	0
T22	830	0	0	0
T28	1504	2	0	0
T33	1465	0	0	0
T39	0	1	0	0
T40	0	3	0	0
T79	0	3	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	5	0	0
T160	0	2	0	0
T161	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T39,T40
1	0	Covered	T8,T6,T9
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91769832	7356	0	0
CgEnOn_A	91769832	5182	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	7356	0	0
T4	12163	16	0	0
T5	25105	21	0	0
T6	3930	1	0	0
T7	45275	1	0	0
T8	426	11	0	0
T9	642	1	0	0
T25	4952	1	0	0
T26	895	1	0	0
T27	1790	1	0	0
T28	726	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91769832	5182	0	0
T2	0	49	0	0
T3	0	78	0	0
T4	12163	0	0	0
T5	25105	0	0	0
T6	3930	0	0	0
T7	45275	0	0	0
T8	426	10	0	0
T9	642	0	0	0
T11	0	12	0	0
T20	0	6	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	4952	0	0	0
T26	895	0	0	0
T27	1790	0	0	0
T28	726	2	0	0
T31	0	9	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T39,T40
1	0	Covered	T8,T6,T9
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	183540877	7426	0	0
CgEnOn_A	183540877	5252	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183540877	7426	0	0
T4	24328	16	0	0
T5	50216	21	0	0
T6	7860	1	0	0
T7	90549	1	0	0
T8	852	10	0	0
T9	1289	1	0	0
T25	9906	1	0	0
T26	1794	1	0	0
T27	3580	1	0	0
T28	1452	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183540877	5252	0	0
T2	0	52	0	0
T3	0	77	0	0
T4	24328	0	0	0
T5	50216	0	0	0
T6	7860	0	0	0
T7	90549	0	0	0
T8	852	9	0	0
T9	1289	0	0	0
T11	0	10	0	0
T20	0	6	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	9906	0	0	0
T26	1794	0	0	0
T27	3580	0	0	0
T28	1452	2	0	0
T31	0	9	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T39,T40
1	0	Covered	T8,T6,T9
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	368246313	7426	0	0
CgEnOn_A	368246313	5240	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368246313	7426	0	0
T4	85657	16	0	0
T5	151841	21	0	0
T6	15827	1	0	0
T7	181232	1	0	0
T8	1782	11	0	0
T9	2375	1	0	0
T25	17534	1	0	0
T26	3236	1	0	0
T27	7295	1	0	0
T28	3011	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	368246313	5240	0	0
T2	0	49	0	0
T3	0	78	0	0
T4	85657	0	0	0
T5	151841	0	0	0
T6	15827	0	0	0
T7	181232	0	0	0
T8	1782	10	0	0
T9	2375	0	0	0
T11	0	9	0	0
T20	0	6	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	17534	0	0	0
T26	3236	0	0	0
T27	7295	0	0	0
T28	3011	2	0	0
T31	0	9	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T39,T40
1	0	Covered	T8,T6,T9
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	189123907	7375	0	0
CgEnOn_A	189123907	5189	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189123907	7375	0	0
T4	42831	16	0	0
T5	75923	21	0	0
T6	7914	1	0	0
T7	113661	1	0	0
T8	891	11	0	0
T9	1187	1	0	0
T25	8767	1	0	0
T26	1618	1	0	0
T27	3647	1	0	0
T28	1504	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189123907	5189	0	0
T2	0	52	0	0
T3	0	79	0	0
T4	42831	0	0	0
T5	75923	0	0	0
T6	7914	0	0	0
T7	113661	0	0	0
T8	891	10	0	0
T9	1187	0	0	0
T11	0	12	0	0
T20	0	6	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	8767	0	0	0
T26	1618	0	0	0
T27	3647	0	0	0
T28	1504	2	0	0
T31	0	6	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Covered	T27,T2,T3
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393998983	4129	0	0
CgEnOn_A	393998983	4127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4129	0	0
T1	97077	0	0	0
T2	122077	63	0	0
T3	768043	53	0	0
T11	0	2	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	4	0	0
T27	7599	2	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	3	0	0
T111	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4127	0	0
T1	97077	0	0	0
T2	122077	63	0	0
T3	768043	53	0	0
T11	0	2	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	4	0	0
T27	7599	2	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	3	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Covered	T27,T2,T3
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393998983	4076	0	0
CgEnOn_A	393998983	4074	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4076	0	0
T1	97077	0	0	0
T2	122077	55	0	0
T3	768043	60	0	0
T11	0	2	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	10	0	0
T27	7599	4	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	5	0	0
T111	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4074	0	0
T1	97077	0	0	0
T2	122077	55	0	0
T3	768043	60	0	0
T11	0	2	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	10	0	0
T27	7599	4	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	5	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Covered	T27,T2,T3
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393998983	4085	0	0
CgEnOn_A	393998983	4083	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4085	0	0
T1	97077	0	0	0
T2	122077	62	0	0
T3	768043	54	0	0
T11	0	3	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	8	0	0
T27	7599	3	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	5	0	0
T111	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4083	0	0
T1	97077	0	0	0
T2	122077	62	0	0
T3	768043	54	0	0
T11	0	3	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	8	0	0
T27	7599	3	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	5	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T28
1	0	Covered	T27,T2,T3
1	1	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	393998983	4099	0	0
CgEnOn_A	393998983	4097	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4099	0	0
T1	97077	0	0	0
T2	122077	52	0	0
T3	768043	52	0	0
T11	0	3	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	7599	4	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	3	0	0
T111	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393998983	4097	0	0
T1	97077	0	0	0
T2	122077	52	0	0
T3	768043	52	0	0
T11	0	3	0	0
T18	91459	0	0	0
T19	4686	0	0	0
T20	1493	0	0	0
T21	21939	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	5	0	0
T27	7599	4	0	0
T28	3044	2	0	0
T33	3052	0	0	0
T110	0	3	0	0
T111	0	1	0	0