Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	619773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3548605

1

T1

100239

T7

16

T18

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1021811	1			T1	27283		T7	14		T18	3
values[0x0]	1446582	1			T1	40146		T7	10		T18	3
values[0x1]	1699985	1			T1	47698		T7	19		T18	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3825461

1

T1

107596

T7

17

T18

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15740	1			T1	504		T4	2		T25	1
valid_sources[0x01]	15426	1			T1	444		T4	3		T25	1
valid_sources[0x02]	15853	1			T1	529		T4	5		T2	46
valid_sources[0x03]	17055	1			T1	318		T4	1		T25	1
valid_sources[0x04]	16329	1			T1	550		T4	5		T25	2
valid_sources[0x05]	16273	1			T1	442		T18	2		T4	1
valid_sources[0x06]	13907	1			T1	322		T4	2		T25	3
valid_sources[0x07]	16277	1			T1	419		T4	2		T2	81
valid_sources[0x08]	17308	1			T1	581		T7	1		T18	1
valid_sources[0x09]	15713	1			T1	319		T4	1		T65	8
valid_sources[0x0a]	16242	1			T1	523		T35	1		T4	4
valid_sources[0x0b]	16085	1			T1	633		T4	2		T82	1
valid_sources[0x0c]	15371	1			T1	283		T4	4		T63	1
valid_sources[0x0d]	16623	1			T1	312		T4	1		T2	302
valid_sources[0x0e]	16252	1			T1	342		T4	3		T28	1
valid_sources[0x0f]	14842	1			T1	444		T22	77		T4	7
valid_sources[0x10]	15015	1			T1	492		T25	1		T2	1
valid_sources[0x11]	17682	1			T1	466		T4	3		T25	2
valid_sources[0x12]	17138	1			T1	508		T5	1		T6	1
valid_sources[0x13]	16205	1			T1	325		T7	3		T4	4
valid_sources[0x14]	15823	1			T1	507		T4	4		T25	1
valid_sources[0x15]	16389	1			T1	417		T35	4		T4	8
valid_sources[0x16]	16064	1			T1	505		T4	2		T63	1
valid_sources[0x17]	17001	1			T1	656		T7	3		T5	1
valid_sources[0x18]	18450	1			T1	365		T4	1		T2	7
valid_sources[0x19]	17026	1			T1	467		T7	1		T5	1
valid_sources[0x1a]	16162	1			T1	381		T4	3		T2	361
valid_sources[0x1b]	15609	1			T1	310		T35	2		T4	4
valid_sources[0x1c]	16525	1			T1	476		T5	1		T4	5
valid_sources[0x1d]	17974	1			T1	503		T4	2		T25	1
valid_sources[0x1e]	15303	1			T1	306		T4	1		T63	1
valid_sources[0x1f]	14844	1			T1	463		T4	4		T26	1
valid_sources[0x20]	16361	1			T1	439		T7	1		T35	2
valid_sources[0x21]	16854	1			T1	344		T7	1		T4	3
valid_sources[0x22]	15311	1			T1	524		T35	2		T4	3
valid_sources[0x23]	16623	1			T1	402		T21	2		T5	1
valid_sources[0x24]	17033	1			T1	438		T4	3		T25	4
valid_sources[0x25]	15665	1			T1	351		T7	1		T4	7
valid_sources[0x26]	17152	1			T1	546		T7	1		T4	4
valid_sources[0x27]	16214	1			T1	352		T5	1		T4	2
valid_sources[0x28]	15576	1			T1	439		T7	2		T4	2
valid_sources[0x29]	15702	1			T1	463		T5	1		T35	3
valid_sources[0x2a]	16459	1			T1	349		T6	1		T4	11
valid_sources[0x2b]	16643	1			T1	422		T5	1		T4	3
valid_sources[0x2c]	18130	1			T1	532		T35	2		T4	2
valid_sources[0x2d]	17203	1			T1	528		T4	1		T63	1
valid_sources[0x2e]	16506	1			T1	489		T4	3		T2	526
valid_sources[0x2f]	14851	1			T1	362		T4	7		T25	2
valid_sources[0x30]	16358	1			T1	596		T7	1		T4	5
valid_sources[0x31]	16712	1			T1	330		T6	1		T4	2
valid_sources[0x32]	15416	1			T1	514		T5	1		T4	6
valid_sources[0x33]	17167	1			T1	447		T4	7		T63	1
valid_sources[0x34]	15781	1			T1	559		T35	2		T4	1
valid_sources[0x35]	15535	1			T1	491		T25	2		T2	221
valid_sources[0x36]	15658	1			T1	480		T4	2		T2	94
valid_sources[0x37]	15869	1			T1	349		T35	1		T4	2
valid_sources[0x38]	16088	1			T1	448		T6	1		T4	2
valid_sources[0x39]	17695	1			T1	380		T4	6		T25	1
valid_sources[0x3a]	16889	1			T1	545		T35	1		T4	4
valid_sources[0x3b]	16125	1			T1	462		T4	2		T26	2
valid_sources[0x3c]	16424	1			T1	639		T21	3		T35	1
valid_sources[0x3d]	16671	1			T1	601		T7	1		T5	1
valid_sources[0x3e]	17570	1			T1	409		T25	1		T26	1
valid_sources[0x3f]	15613	1			T1	388		T4	7		T25	3
valid_sources[0x40]	16434	1			T1	364		T4	4		T25	1
valid_sources[0x41]	15933	1			T1	356		T7	1		T4	6
valid_sources[0x42]	16217	1			T1	506		T5	1		T4	3
valid_sources[0x43]	16233	1			T1	457		T4	4		T86	3
valid_sources[0x44]	15164	1			T1	511		T5	1		T4	1
valid_sources[0x45]	17421	1			T1	442		T18	3		T5	1
valid_sources[0x46]	15032	1			T1	387		T7	2		T35	1
valid_sources[0x47]	15051	1			T1	380		T5	1		T4	4
valid_sources[0x48]	15473	1			T1	504		T4	1		T82	1
valid_sources[0x49]	16449	1			T1	460		T4	5		T25	2
valid_sources[0x4a]	16230	1			T1	567		T21	1		T4	4
valid_sources[0x4b]	15870	1			T1	519		T4	1		T25	1
valid_sources[0x4c]	16233	1			T1	309		T7	1		T35	1
valid_sources[0x4d]	16103	1			T1	526		T4	3		T86	3
valid_sources[0x4e]	16321	1			T1	356		T4	3		T63	1
valid_sources[0x4f]	16287	1			T1	446		T4	7		T25	3
valid_sources[0x50]	16160	1			T1	446		T35	1		T4	1
valid_sources[0x51]	15411	1			T1	427		T4	1		T2	367
valid_sources[0x52]	16901	1			T1	484		T4	1		T25	2
valid_sources[0x53]	16458	1			T1	559		T21	1		T4	2
valid_sources[0x54]	16697	1			T1	453		T4	1		T25	2
valid_sources[0x55]	15880	1			T1	465		T35	1		T4	1
valid_sources[0x56]	17734	1			T1	397		T4	8		T29	15
valid_sources[0x57]	15642	1			T1	432		T25	3		T26	3
valid_sources[0x58]	17299	1			T1	511		T5	1		T6	1
valid_sources[0x59]	16183	1			T1	639		T4	4		T25	1
valid_sources[0x5a]	15392	1			T1	389		T5	1		T4	9
valid_sources[0x5b]	18157	1			T1	426		T5	2		T4	1
valid_sources[0x5c]	14695	1			T1	614		T35	1		T4	1
valid_sources[0x5d]	15987	1			T1	572		T35	1		T4	1
valid_sources[0x5e]	16620	1			T1	409		T4	2		T25	3
valid_sources[0x5f]	16939	1			T1	329		T4	7		T25	1
valid_sources[0x60]	16890	1			T1	591		T4	3		T2	387
valid_sources[0x61]	16527	1			T1	545		T4	7		T2	501
valid_sources[0x62]	15319	1			T1	543		T4	3		T25	2
valid_sources[0x63]	16417	1			T1	422		T4	1		T25	1
valid_sources[0x64]	17288	1			T1	458		T21	1		T6	3
valid_sources[0x65]	16703	1			T1	364		T4	7		T63	2
valid_sources[0x66]	16954	1			T1	515		T4	4		T25	6
valid_sources[0x67]	15181	1			T1	454		T5	1		T25	2
valid_sources[0x68]	15969	1			T1	475		T7	2		T21	1
valid_sources[0x69]	16746	1			T1	561		T4	6		T25	3
valid_sources[0x6a]	15217	1			T1	467		T4	5		T26	2
valid_sources[0x6b]	16212	1			T1	414		T19	40		T4	7
valid_sources[0x6c]	17794	1			T1	365		T5	1		T4	1
valid_sources[0x6d]	14795	1			T1	443		T5	2		T4	3
valid_sources[0x6e]	16340	1			T1	479		T4	4		T25	2
valid_sources[0x6f]	16544	1			T1	329		T83	8		T2	64
valid_sources[0x70]	16387	1			T1	377		T4	3		T25	1
valid_sources[0x71]	16772	1			T1	433		T4	4		T25	3
valid_sources[0x72]	15969	1			T1	610		T35	1		T4	3
valid_sources[0x73]	15575	1			T1	544		T35	1		T4	1
valid_sources[0x74]	17235	1			T1	372		T4	3		T25	1
valid_sources[0x75]	15785	1			T1	362		T4	1		T25	2
valid_sources[0x76]	15225	1			T1	407		T35	2		T4	3
valid_sources[0x77]	16938	1			T1	673		T4	4		T25	1
valid_sources[0x78]	15143	1			T1	352		T4	5		T2	728
valid_sources[0x79]	16189	1			T1	526		T4	3		T25	4
valid_sources[0x7a]	16441	1			T1	391		T25	3		T2	393
valid_sources[0x7b]	16845	1			T1	375		T4	3		T25	3
valid_sources[0x7c]	16416	1			T1	269		T4	3		T26	1
valid_sources[0x7d]	15929	1			T1	366		T4	4		T25	2
valid_sources[0x7e]	16100	1			T1	372		T4	2		T25	1
valid_sources[0x7f]	15425	1			T1	494		T21	3		T6	7
valid_sources[0x80]	16746	1			T1	350		T35	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

893502

1

T1

24951

T7

6

T18

1

values[0x0]

all_enables

biggest_size

1351225

1

T1

38153

T7

3

T19

8

values[0x1]

all_enables

biggest_size

1303878

1

T1

37135

T7

7

T18

1