Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T20
0	1	Covered	T1,T35,T65
1	0	Covered	T1,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T4
1	0	Covered	T8,T20,T36
1	1	Covered	T1,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1004120439	14088	0	0
GateOpen_A	1004120439	20658	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004120439	14088	0	0
T1	1712286	303	0	0
T2	0	387	0	0
T5	43862	0	0	0
T6	19623	0	0	0
T7	6590	0	0	0
T8	8430	19	0	0
T18	3464	0	0	0
T19	4998	0	0	0
T20	5796	24	0	0
T21	3639	0	0	0
T22	5018	0	0	0
T36	0	18	0	0
T65	0	10	0	0
T109	0	4	0	0
T165	0	7	0	0
T166	0	8	0	0
T172	0	23	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004120439	20658	0	0
T1	1712286	327	0	0
T4	0	76	0	0
T5	43862	0	0	0
T6	19623	4	0	0
T7	6590	4	0	0
T8	8430	23	0	0
T18	3464	0	0	0
T19	4998	0	0	0
T20	5796	28	0	0
T21	3639	0	0	0
T22	5018	0	0	0
T36	0	22	0	0
T63	0	4	0	0
T64	0	4	0	0
T65	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T20
0	1	Covered	T1,T35,T65
1	0	Covered	T1,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T4
1	0	Covered	T8,T20,T36
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	110772855	3362	0	0
GateOpen_A	110772855	5004	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772855	3362	0	0
T1	315412	75	0	0
T2	0	92	0	0
T5	4854	0	0	0
T6	1847	0	0	0
T7	784	0	0	0
T8	921	5	0	0
T18	396	0	0	0
T19	548	0	0	0
T20	630	6	0	0
T21	411	0	0	0
T22	535	0	0	0
T36	0	4	0	0
T65	0	2	0	0
T109	0	1	0	0
T165	0	2	0	0
T166	0	2	0	0
T172	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772855	5004	0	0
T1	315412	81	0	0
T4	0	19	0	0
T5	4854	0	0	0
T6	1847	1	0	0
T7	784	1	0	0
T8	921	6	0	0
T18	396	0	0	0
T19	548	0	0	0
T20	630	7	0	0
T21	411	0	0	0
T22	535	0	0	0
T36	0	5	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T20
0	1	Covered	T1,T35,T65
1	0	Covered	T1,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T4
1	0	Covered	T8,T20,T36
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	221546556	3566	0	0
GateOpen_A	221546556	5208	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546556	3566	0	0
T1	630827	76	0	0
T2	0	100	0	0
T5	9707	0	0	0
T6	3694	0	0	0
T7	1570	0	0	0
T8	1841	5	0	0
T18	791	0	0	0
T19	1096	0	0	0
T20	1259	6	0	0
T21	824	0	0	0
T22	1070	0	0	0
T36	0	4	0	0
T65	0	2	0	0
T109	0	1	0	0
T165	0	2	0	0
T166	0	2	0	0
T172	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546556	5208	0	0
T1	630827	82	0	0
T4	0	19	0	0
T5	9707	0	0	0
T6	3694	1	0	0
T7	1570	1	0	0
T8	1841	6	0	0
T18	791	0	0	0
T19	1096	0	0	0
T20	1259	7	0	0
T21	824	0	0	0
T22	1070	0	0	0
T36	0	5	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T20
0	1	Covered	T1,T35,T65
1	0	Covered	T1,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T4
1	0	Covered	T8,T20,T36
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	444528408	3579	0	0
GateOpen_A	444528408	5222	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444528408	3579	0	0
T1	126181	78	0	0
T2	0	98	0	0
T5	19534	0	0	0
T6	7468	0	0	0
T7	2824	0	0	0
T8	3718	5	0	0
T18	1518	0	0	0
T19	2236	0	0	0
T20	2568	6	0	0
T21	1603	0	0	0
T22	2275	0	0	0
T36	0	4	0	0
T65	0	2	0	0
T109	0	1	0	0
T165	0	2	0	0
T166	0	2	0	0
T172	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444528408	5222	0	0
T1	126181	84	0	0
T4	0	19	0	0
T5	19534	0	0	0
T6	7468	1	0	0
T7	2824	1	0	0
T8	3718	6	0	0
T18	1518	0	0	0
T19	2236	0	0	0
T20	2568	7	0	0
T21	1603	0	0	0
T22	2275	0	0	0
T36	0	5	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T20
0	1	Covered	T1,T35,T65
1	0	Covered	T1,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T4
1	0	Covered	T8,T20,T36
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	227272620	3581	0	0
GateOpen_A	227272620	5224	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227272620	3581	0	0
T1	639866	74	0	0
T2	0	97	0	0
T5	9767	0	0	0
T6	6614	0	0	0
T7	1412	0	0	0
T8	1950	4	0	0
T18	759	0	0	0
T19	1118	0	0	0
T20	1339	6	0	0
T21	801	0	0	0
T22	1138	0	0	0
T36	0	6	0	0
T65	0	4	0	0
T109	0	1	0	0
T165	0	1	0	0
T166	0	2	0	0
T172	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227272620	5224	0	0
T1	639866	80	0	0
T4	0	19	0	0
T5	9767	0	0	0
T6	6614	1	0	0
T7	1412	1	0	0
T8	1950	5	0	0
T18	759	0	0	0
T19	1118	0	0	0
T20	1339	7	0	0
T21	801	0	0	0
T22	1138	0	0	0
T36	0	7	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	4	0	0