Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	771733940	77870	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771733940	77870	0	0
T1	1551625	1003	0	0
T2	0	723	0	0
T3	0	639	0	0
T5	101735	0	0	0
T6	44090	0	0	0
T7	9855	0	0	0
T8	5620	0	0	0
T11	0	658	0	0
T12	0	837	0	0
T13	0	731	0	0
T14	0	156	0	0
T15	0	809	0	0
T16	0	758	0	0
T17	0	149	0	0
T18	7510	0	0	0
T19	11300	0	0	0
T20	7460	0	0	0
T21	7930	0	0	0
T22	11370	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154346788	11568	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	11568	0	0
T1	310325	161	0	0
T2	0	117	0	0
T3	0	80	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T11	0	87	0	0
T12	0	124	0	0
T13	0	93	0	0
T14	0	29	0	0
T15	0	157	0	0
T16	0	121	0	0
T17	0	24	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154346788	11414	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	11414	0	0
T1	310325	159	0	0
T2	0	113	0	0
T3	0	91	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T11	0	87	0	0
T12	0	106	0	0
T13	0	104	0	0
T14	0	29	0	0
T15	0	157	0	0
T16	0	118	0	0
T17	0	24	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154346788	15754	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	15754	0	0
T1	310325	200	0	0
T2	0	146	0	0
T3	0	128	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T11	0	133	0	0
T12	0	165	0	0
T13	0	143	0	0
T14	0	30	0	0
T15	0	157	0	0
T16	0	152	0	0
T17	0	30	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154346788	15640	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	15640	0	0
T1	310325	205	0	0
T2	0	146	0	0
T3	0	126	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T11	0	133	0	0
T12	0	169	0	0
T13	0	145	0	0
T14	0	30	0	0
T15	0	157	0	0
T16	0	153	0	0
T17	0	30	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154346788	23494	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	23494	0	0
T1	310325	278	0	0
T2	0	201	0	0
T3	0	214	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T11	0	218	0	0
T12	0	273	0	0
T13	0	246	0	0
T14	0	38	0	0
T15	0	181	0	0
T16	0	214	0	0
T17	0	41	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0