Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Unreachable
1	0	Covered	T1,T4,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	154346788	152165396	0	0
AllClkBypReqTrue_A	154346788	138709	0	0
IoClkBypReqFalse_A	154346788	152078875	0	2415
IoClkBypReqTrue_A	154346788	220560	0	0
LcClkBypAckFalse_A	154346788	152175655	0	0
LcClkBypAckTrue_A	154346788	128450	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	152165396	0	0
T1	310325	309333	0	0
T5	20347	20178	0	0
T6	8818	8672	0	0
T7	1971	1673	0	0
T8	1124	1083	0	0
T18	1502	1243	0	0
T19	2260	1987	0	0
T20	1492	1397	0	0
T21	1586	1479	0	0
T22	2274	2042	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	138709	0	0
T1	310325	1912	0	0
T2	0	2157	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	212	0	0
T8	1124	0	0	0
T18	1502	111	0	0
T19	2260	52	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T64	0	76	0	0
T82	0	177	0	0
T84	0	376	0	0
T86	0	23	0	0
T107	0	127	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	152078875	0	2415
T1	310325	309214	0	3
T5	20347	20176	0	3
T6	8818	8670	0	3
T7	1971	1460	0	3
T8	1124	1081	0	3
T18	1502	1277	0	3
T19	2260	2037	0	3
T20	1492	1395	0	3
T21	1586	1365	0	3
T22	2274	2040	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	220560	0	0
T1	310325	3087	0	0
T2	0	3604	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	423	0	0
T8	1124	0	0	0
T18	1502	75	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	112	0	0
T22	2274	0	0	0
T64	0	86	0	0
T82	0	264	0	0
T84	0	612	0	0
T86	0	451	0	0
T108	0	30	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	152175655	0	0
T1	310325	309326	0	0
T5	20347	20178	0	0
T6	8818	8672	0	0
T7	1971	1637	0	0
T8	1124	1083	0	0
T18	1502	1284	0	0
T19	2260	2039	0	0
T20	1492	1397	0	0
T21	1586	1376	0	0
T22	2274	2042	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	128450	0	0
T1	310325	1981	0	0
T2	0	2342	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	248	0	0
T8	1124	0	0	0
T18	1502	70	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	103	0	0
T22	2274	0	0	0
T64	0	43	0	0
T82	0	102	0	0
T84	0	454	0	0
T86	0	189	0	0
T107	0	92	0	0