Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1893920320	15525	0	0
TransStop_A	1893920320	7879	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1893920320	15525	0	0
T1	534412	352	0	0
T2	0	356	0	0
T5	81392	0	0	0
T6	55116	0	0	0
T7	11764	0	0	0
T8	15744	0	0	0
T11	0	63	0	0
T18	6324	0	0	0
T19	9320	0	0	0
T20	11076	0	0	0
T21	6680	0	0	0
T22	9480	17	0	0
T35	0	4	0	0
T63	0	10	0	0
T83	0	31	0	0
T85	0	18	0	0
T109	0	4	0	0
T110	0	23	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1893920320	7879	0	0
T1	534412	166	0	0
T2	0	186	0	0
T5	81392	0	0	0
T6	55116	0	0	0
T7	11764	0	0	0
T8	15744	0	0	0
T11	0	34	0	0
T12	0	76	0	0
T18	6324	0	0	0
T19	9320	0	0	0
T20	11076	0	0	0
T21	6680	0	0	0
T22	9480	7	0	0
T63	0	4	0	0
T83	0	20	0	0
T85	0	11	0	0
T109	0	4	0	0
T110	0	8	0	0
T111	0	16	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	473480080	3859	0	0
TransStop_A	473480080	1947	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	3859	0	0
T1	133603	96	0	0
T2	0	82	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	14	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	5	0	0
T35	0	1	0	0
T63	0	3	0	0
T83	0	3	0	0
T85	0	4	0	0
T109	0	1	0	0
T110	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	1947	0	0
T1	133603	43	0	0
T2	0	46	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	8	0	0
T12	0	17	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	2	0	0
T63	0	1	0	0
T83	0	2	0	0
T85	0	2	0	0
T109	0	1	0	0
T111	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	473480080	3853	0	0
TransStop_A	473480080	1980	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	3853	0	0
T1	133603	80	0	0
T2	0	90	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	13	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	5	0	0
T35	0	1	0	0
T63	0	3	0	0
T83	0	8	0	0
T85	0	5	0	0
T109	0	1	0	0
T110	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	1980	0	0
T1	133603	34	0	0
T2	0	50	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	9	0	0
T12	0	23	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	2	0	0
T63	0	2	0	0
T83	0	5	0	0
T85	0	4	0	0
T109	0	1	0	0
T110	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	473480080	3900	0	0
TransStop_A	473480080	1977	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	3900	0	0
T1	133603	87	0	0
T2	0	91	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	14	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	4	0	0
T35	0	1	0	0
T63	0	1	0	0
T83	0	11	0	0
T85	0	6	0	0
T109	0	1	0	0
T110	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	1977	0	0
T1	133603	47	0	0
T2	0	42	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	8	0	0
T12	0	17	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	1	0	0
T83	0	7	0	0
T85	0	4	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	473480080	3913	0	0
TransStop_A	473480080	1975	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	3913	0	0
T1	133603	89	0	0
T2	0	93	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	22	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	3	0	0
T35	0	1	0	0
T63	0	3	0	0
T83	0	9	0	0
T85	0	3	0	0
T109	0	1	0	0
T110	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473480080	1975	0	0
T1	133603	42	0	0
T2	0	48	0	0
T5	20348	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	0	0	0
T11	0	9	0	0
T12	0	19	0	0
T18	1581	0	0	0
T19	2330	0	0	0
T20	2769	0	0	0
T21	1670	0	0	0
T22	2370	2	0	0
T63	0	1	0	0
T83	0	6	0	0
T85	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0