SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 308693576 | 304612880 | 0 | 0 |
gen_flops.OutputDelay_A | 308693576 | 304598520 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
T21 | 2 | 2 | 0 | 0 |
T22 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 308693576 | 304612880 | 0 | 0 |
T1 | 620650 | 619052 | 0 | 0 |
T5 | 40694 | 40358 | 0 | 0 |
T6 | 17636 | 17346 | 0 | 0 |
T7 | 3942 | 3772 | 0 | 0 |
T8 | 2248 | 2168 | 0 | 0 |
T18 | 3004 | 2710 | 0 | 0 |
T19 | 4520 | 4080 | 0 | 0 |
T20 | 2984 | 2796 | 0 | 0 |
T21 | 3172 | 2960 | 0 | 0 |
T22 | 4548 | 4086 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 308693576 | 304598520 | 0 | 4830 |
T1 | 620650 | 619044 | 0 | 6 |
T5 | 40694 | 40352 | 0 | 6 |
T6 | 17636 | 17340 | 0 | 6 |
T7 | 3942 | 3766 | 0 | 6 |
T8 | 2248 | 2162 | 0 | 6 |
T18 | 3004 | 2704 | 0 | 6 |
T19 | 4520 | 4074 | 0 | 6 |
T20 | 2984 | 2790 | 0 | 6 |
T21 | 3172 | 2954 | 0 | 6 |
T22 | 4548 | 4080 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 154346788 | 152306440 | 0 | 0 |
gen_flops.OutputDelay_A | 154346788 | 152299260 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 154346788 | 152306440 | 0 | 0 |
T1 | 310325 | 309526 | 0 | 0 |
T5 | 20347 | 20179 | 0 | 0 |
T6 | 8818 | 8673 | 0 | 0 |
T7 | 1971 | 1886 | 0 | 0 |
T8 | 1124 | 1084 | 0 | 0 |
T18 | 1502 | 1355 | 0 | 0 |
T19 | 2260 | 2040 | 0 | 0 |
T20 | 1492 | 1398 | 0 | 0 |
T21 | 1586 | 1480 | 0 | 0 |
T22 | 2274 | 2043 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 154346788 | 152299260 | 0 | 2415 |
T1 | 310325 | 309522 | 0 | 3 |
T5 | 20347 | 20176 | 0 | 3 |
T6 | 8818 | 8670 | 0 | 3 |
T7 | 1971 | 1883 | 0 | 3 |
T8 | 1124 | 1081 | 0 | 3 |
T18 | 1502 | 1352 | 0 | 3 |
T19 | 2260 | 2037 | 0 | 3 |
T20 | 1492 | 1395 | 0 | 3 |
T21 | 1586 | 1477 | 0 | 3 |
T22 | 2274 | 2040 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 154346788 | 152306440 | 0 | 0 |
gen_flops.OutputDelay_A | 154346788 | 152299260 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 154346788 | 152306440 | 0 | 0 |
T1 | 310325 | 309526 | 0 | 0 |
T5 | 20347 | 20179 | 0 | 0 |
T6 | 8818 | 8673 | 0 | 0 |
T7 | 1971 | 1886 | 0 | 0 |
T8 | 1124 | 1084 | 0 | 0 |
T18 | 1502 | 1355 | 0 | 0 |
T19 | 2260 | 2040 | 0 | 0 |
T20 | 1492 | 1398 | 0 | 0 |
T21 | 1586 | 1480 | 0 | 0 |
T22 | 2274 | 2043 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 154346788 | 152299260 | 0 | 2415 |
T1 | 310325 | 309522 | 0 | 3 |
T5 | 20347 | 20176 | 0 | 3 |
T6 | 8818 | 8670 | 0 | 3 |
T7 | 1971 | 1883 | 0 | 3 |
T8 | 1124 | 1081 | 0 | 3 |
T18 | 1502 | 1352 | 0 | 3 |
T19 | 2260 | 2037 | 0 | 3 |
T20 | 1492 | 1395 | 0 | 3 |
T21 | 1586 | 1477 | 0 | 3 |
T22 | 2274 | 2040 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |