Line Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Module :
prim_subreg_shadow
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T53 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T53 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T51,T52,T53 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T51,T52,T53 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Module :
prim_subreg_shadow
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10100 |
10100 |
0 |
0 |
T1 |
10 |
10 |
0 |
0 |
T5 |
10 |
10 |
0 |
0 |
T6 |
10 |
10 |
0 |
0 |
T7 |
10 |
10 |
0 |
0 |
T8 |
10 |
10 |
0 |
0 |
T18 |
10 |
10 |
0 |
0 |
T19 |
10 |
10 |
0 |
0 |
T20 |
10 |
10 |
0 |
0 |
T21 |
10 |
10 |
0 |
0 |
T22 |
10 |
10 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3691778 |
3684864 |
0 |
0 |
T5 |
128410 |
127528 |
0 |
0 |
T6 |
66800 |
65492 |
0 |
0 |
T7 |
19056 |
18380 |
0 |
0 |
T8 |
24728 |
23808 |
0 |
0 |
T18 |
10082 |
9144 |
0 |
0 |
T19 |
14648 |
13360 |
0 |
0 |
T20 |
17126 |
15958 |
0 |
0 |
T21 |
10612 |
10004 |
0 |
0 |
T22 |
14770 |
13452 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T54 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T54 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T54 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T52,T54,T55 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T52,T54,T55 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446790593 |
442456488 |
0 |
0 |
T1 |
126181 |
125903 |
0 |
0 |
T5 |
19533 |
19371 |
0 |
0 |
T6 |
7467 |
7250 |
0 |
0 |
T7 |
2823 |
2702 |
0 |
0 |
T8 |
3718 |
3570 |
0 |
0 |
T18 |
1517 |
1369 |
0 |
0 |
T19 |
2236 |
2019 |
0 |
0 |
T20 |
2568 |
2379 |
0 |
0 |
T21 |
1603 |
1495 |
0 |
0 |
T22 |
2274 |
2043 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T54 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T54 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T54 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T52,T54,T55 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T52,T54,T55 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446790593 |
442456488 |
0 |
0 |
T1 |
126181 |
125903 |
0 |
0 |
T5 |
19533 |
19371 |
0 |
0 |
T6 |
7467 |
7250 |
0 |
0 |
T7 |
2823 |
2702 |
0 |
0 |
T8 |
3718 |
3570 |
0 |
0 |
T18 |
1517 |
1369 |
0 |
0 |
T19 |
2236 |
2019 |
0 |
0 |
T20 |
2568 |
2379 |
0 |
0 |
T21 |
1603 |
1495 |
0 |
0 |
T22 |
2274 |
2043 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T54 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T54 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T51,T52,T53 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T51,T52,T53 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
222632250 |
221551852 |
0 |
0 |
T1 |
630827 |
630052 |
0 |
0 |
T5 |
9706 |
9685 |
0 |
0 |
T6 |
3694 |
3625 |
0 |
0 |
T7 |
1570 |
1549 |
0 |
0 |
T8 |
1840 |
1785 |
0 |
0 |
T18 |
790 |
728 |
0 |
0 |
T19 |
1095 |
1033 |
0 |
0 |
T20 |
1258 |
1189 |
0 |
0 |
T21 |
823 |
802 |
0 |
0 |
T22 |
1070 |
1022 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T56 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T56 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T51,T52,T53 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T51,T52,T53 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
222632250 |
221551852 |
0 |
0 |
T1 |
630827 |
630052 |
0 |
0 |
T5 |
9706 |
9685 |
0 |
0 |
T6 |
3694 |
3625 |
0 |
0 |
T7 |
1570 |
1549 |
0 |
0 |
T8 |
1840 |
1785 |
0 |
0 |
T18 |
790 |
728 |
0 |
0 |
T19 |
1095 |
1033 |
0 |
0 |
T20 |
1258 |
1189 |
0 |
0 |
T21 |
823 |
802 |
0 |
0 |
T22 |
1070 |
1022 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T53 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T53 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T52,T53,T54 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T52,T53,T54 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111315494 |
110775412 |
0 |
0 |
T1 |
315412 |
315025 |
0 |
0 |
T5 |
4853 |
4843 |
0 |
0 |
T6 |
1847 |
1813 |
0 |
0 |
T7 |
783 |
773 |
0 |
0 |
T8 |
920 |
892 |
0 |
0 |
T18 |
395 |
364 |
0 |
0 |
T19 |
547 |
516 |
0 |
0 |
T20 |
629 |
595 |
0 |
0 |
T21 |
410 |
400 |
0 |
0 |
T22 |
535 |
511 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T53,T54 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T53,T54 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T52,T53,T54 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T52,T53,T54 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111315494 |
110775412 |
0 |
0 |
T1 |
315412 |
315025 |
0 |
0 |
T5 |
4853 |
4843 |
0 |
0 |
T6 |
1847 |
1813 |
0 |
0 |
T7 |
783 |
773 |
0 |
0 |
T8 |
920 |
892 |
0 |
0 |
T18 |
395 |
364 |
0 |
0 |
T19 |
547 |
516 |
0 |
0 |
T20 |
629 |
595 |
0 |
0 |
T21 |
410 |
400 |
0 |
0 |
T22 |
535 |
511 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T55 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T54 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T51,T52,T54 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T51,T52,T54 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
475836606 |
471277833 |
0 |
0 |
T1 |
133603 |
133255 |
0 |
0 |
T5 |
20347 |
20179 |
0 |
0 |
T6 |
13779 |
13553 |
0 |
0 |
T7 |
2941 |
2815 |
0 |
0 |
T8 |
3936 |
3781 |
0 |
0 |
T18 |
1580 |
1426 |
0 |
0 |
T19 |
2329 |
2103 |
0 |
0 |
T20 |
2769 |
2571 |
0 |
0 |
T21 |
1669 |
1557 |
0 |
0 |
T22 |
2369 |
2129 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T55 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T54 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T55 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T52,T54,T57 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T52,T54,T57 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T54 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
475836606 |
471277833 |
0 |
0 |
T1 |
133603 |
133255 |
0 |
0 |
T5 |
20347 |
20179 |
0 |
0 |
T6 |
13779 |
13553 |
0 |
0 |
T7 |
2941 |
2815 |
0 |
0 |
T8 |
3936 |
3781 |
0 |
0 |
T18 |
1580 |
1426 |
0 |
0 |
T19 |
2329 |
2103 |
0 |
0 |
T20 |
2769 |
2571 |
0 |
0 |
T21 |
1669 |
1557 |
0 |
0 |
T22 |
2369 |
2129 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T52,T53 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T52,T53 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T51,T53,T56 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T51,T53,T56 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228403573 |
226222652 |
0 |
0 |
T1 |
639866 |
638197 |
0 |
0 |
T5 |
9766 |
9686 |
0 |
0 |
T6 |
6613 |
6505 |
0 |
0 |
T7 |
1411 |
1351 |
0 |
0 |
T8 |
1950 |
1876 |
0 |
0 |
T18 |
759 |
685 |
0 |
0 |
T19 |
1117 |
1009 |
0 |
0 |
T20 |
1339 |
1245 |
0 |
0 |
T21 |
801 |
748 |
0 |
0 |
T22 |
1137 |
1021 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T51,T53,T54 |
1 | 1 | Covered | T1,T5,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T7,T8 |
0 | 1 | Covered | T51,T52,T53 |
1 | 0 | Covered | T1,T4,T2 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T51,T53,T54 |
1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T7,T8 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | 1 | Covered | T51,T52,T53 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T5,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T5,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T5,T6 |
1 | Covered | T1,T7,T8 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T51,T52,T53 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T7,T8 |
1 | Covered | T51,T52,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T8 |
0 |
Covered |
T1,T5,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T7,T8 |
0 |
1 |
- |
Covered |
T1,T5,T6 |
0 |
0 |
1 |
Covered |
T1,T4,T2 |
0 |
0 |
0 |
Covered |
T1,T7,T8 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228403573 |
226222652 |
0 |
0 |
T1 |
639866 |
638197 |
0 |
0 |
T5 |
9766 |
9686 |
0 |
0 |
T6 |
6613 |
6505 |
0 |
0 |
T7 |
1411 |
1351 |
0 |
0 |
T8 |
1950 |
1876 |
0 |
0 |
T18 |
759 |
685 |
0 |
0 |
T19 |
1117 |
1009 |
0 |
0 |
T20 |
1339 |
1245 |
0 |
0 |
T21 |
801 |
748 |
0 |
0 |
T22 |
1137 |
1021 |
0 |
0 |