Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	154346788	19814608	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	19814608	0	58
T1	310325	125785	0	0
T2	0	837621	0	0
T3	0	73051	0	1
T5	20347	1359	0	1
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T11	0	81703	0	0
T12	0	93684	0	0
T13	0	85215	0	1
T14	0	6669	0	0
T15	0	196449	0	0
T17	0	0	0	1
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T23	0	940	0	1
T24	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1