Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	155286890	5178997	0	0
clk_enables_rd_A	155286890	35578	0	0
clk_hints_rd_A	155286890	31259	0	0
extclk_ctrl_rd_A	155286890	41535	0	0
extclk_ctrl_regwen_rd_A	155286890	30740	0	0
jitter_enable_rd_A	155286890	44320	0	0
jitter_regwen_rd_A	155286890	32938	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	5178997	0	0
T1	310325	155927	0	0
T2	0	106789	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	0	0	0
T8	1124	0	0	0
T12	0	87267	0	0
T15	0	44832	0	0
T16	0	97845	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T58	0	135157	0	0
T59	0	51852	0	0
T60	0	40914	0	0
T61	0	233019	0	0
T62	0	150848	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	35578	0	0
T33	0	4791	0	0
T34	0	2927	0	0
T59	192171	1145	0	0
T60	0	1509	0	0
T71	12476	0	0	0
T133	0	1452	0	0
T134	0	2304	0	0
T135	0	1712	0	0
T136	0	4453	0	0
T137	0	15	0	0
T138	0	3216	0	0
T139	1721	0	0	0
T140	1745	0	0	0
T141	8192	0	0	0
T142	1733	0	0	0
T143	2807	0	0	0
T144	2262	0	0	0
T145	1198	0	0	0
T146	1669	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	31259	0	0
T33	0	4250	0	0
T59	192171	805	0	0
T60	0	1481	0	0
T71	12476	0	0	0
T133	0	1219	0	0
T134	0	1829	0	0
T135	0	1440	0	0
T136	0	3765	0	0
T137	0	23	0	0
T139	1721	0	0	0
T140	1745	0	0	0
T141	8192	0	0	0
T142	1733	0	0	0
T143	2807	0	0	0
T144	2262	0	0	0
T145	1198	0	0	0
T146	1669	0	0	0
T147	0	2	0	0
T148	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	41535	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T7	1971	53	0	0
T8	1124	0	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	0	0	0
T21	1586	26	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T84	0	45	0	0
T97	0	6	0	0
T149	0	21	0	0
T150	0	54	0	0
T151	0	16	0	0
T152	0	51	0	0
T153	0	16	0	0
T154	0	71	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	30740	0	0
T17	34864	0	0	0
T24	58461	0	0	0
T43	0	10	0	0
T58	384471	0	0	0
T59	0	949	0	0
T60	0	1587	0	0
T69	4214	0	0	0
T97	8889	4	0	0
T133	0	1368	0	0
T134	0	1782	0	0
T135	0	1484	0	0
T155	0	49	0	0
T156	0	32	0	0
T157	0	13	0	0
T158	33815	0	0	0
T159	894	0	0	0
T160	2151	0	0	0
T161	1383	0	0	0
T162	2582	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	44320	0	0
T4	29597	0	0	0
T25	180044	0	0	0
T28	1321	0	0	0
T35	2861	51	0	0
T36	1220	0	0	0
T59	0	1293	0	0
T60	0	1608	0	0
T63	1785	0	0	0
T64	1216	0	0	0
T65	714	0	0	0
T82	1732	0	0	0
T83	2715	0	0	0
T133	0	2075	0	0
T134	0	2788	0	0
T135	0	2040	0	0
T136	0	5964	0	0
T147	0	100	0	0
T148	0	53	0	0
T163	0	62	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155286890	32938	0	0
T33	0	5128	0	0
T34	0	2917	0	0
T59	192171	894	0	0
T60	0	1417	0	0
T71	12476	0	0	0
T133	0	1403	0	0
T134	0	2132	0	0
T135	0	1832	0	0
T136	0	4037	0	0
T138	0	2732	0	0
T139	1721	0	0	0
T140	1745	0	0	0
T141	8192	0	0	0
T142	1733	0	0	0
T143	2807	0	0	0
T144	2262	0	0	0
T145	1198	0	0	0
T146	1669	0	0	0
T164	0	1580	0	0