Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T18
1	0	Covered	T1,T7,T82
1	1	Covered	T1,T7,T18

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	444528408	4784	0	0
g_div2.Div2Whole_A	444528408	5512	0	0
g_div4.Div4Stepped_A	221546556	4683	0	0
g_div4.Div4Whole_A	221546556	5256	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444528408	4784	0	0
T1	126181	91	0	0
T2	0	84	0	0
T5	19534	0	0	0
T6	7468	0	0	0
T7	2824	9	0	0
T8	3718	0	0	0
T18	1518	2	0	0
T19	2236	0	0	0
T20	2568	0	0	0
T21	1603	3	0	0
T22	2275	0	0	0
T64	0	2	0	0
T82	0	5	0	0
T84	0	13	0	0
T86	0	8	0	0
T107	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444528408	5512	0	0
T1	126181	98	0	0
T2	0	91	0	0
T5	19534	0	0	0
T6	7468	0	0	0
T7	2824	9	0	0
T8	3718	0	0	0
T18	1518	3	0	0
T19	2236	3	0	0
T20	2568	0	0	0
T21	1603	3	0	0
T22	2275	0	0	0
T64	0	3	0	0
T82	0	5	0	0
T84	0	13	0	0
T86	0	12	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546556	4683	0	0
T1	630827	90	0	0
T2	0	84	0	0
T5	9707	0	0	0
T6	3694	0	0	0
T7	1570	9	0	0
T8	1841	0	0	0
T18	791	2	0	0
T19	1096	0	0	0
T20	1259	0	0	0
T21	824	3	0	0
T22	1070	0	0	0
T64	0	2	0	0
T82	0	5	0	0
T84	0	13	0	0
T86	0	8	0	0
T107	0	5	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546556	5256	0	0
T1	630827	97	0	0
T2	0	91	0	0
T5	9707	0	0	0
T6	3694	0	0	0
T7	1570	9	0	0
T8	1841	0	0	0
T18	791	2	0	0
T19	1096	3	0	0
T20	1259	0	0	0
T21	824	3	0	0
T22	1070	0	0	0
T64	0	3	0	0
T82	0	4	0	0
T84	0	13	0	0
T86	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T18
1	0	Covered	T1,T7,T82
1	1	Covered	T1,T7,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	444528408	4784	0	0
g_div2.Div2Whole_A	444528408	5512	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444528408	4784	0	0
T1	126181	91	0	0
T2	0	84	0	0
T5	19534	0	0	0
T6	7468	0	0	0
T7	2824	9	0	0
T8	3718	0	0	0
T18	1518	2	0	0
T19	2236	0	0	0
T20	2568	0	0	0
T21	1603	3	0	0
T22	2275	0	0	0
T64	0	2	0	0
T82	0	5	0	0
T84	0	13	0	0
T86	0	8	0	0
T107	0	5	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444528408	5512	0	0
T1	126181	98	0	0
T2	0	91	0	0
T5	19534	0	0	0
T6	7468	0	0	0
T7	2824	9	0	0
T8	3718	0	0	0
T18	1518	3	0	0
T19	2236	3	0	0
T20	2568	0	0	0
T21	1603	3	0	0
T22	2275	0	0	0
T64	0	3	0	0
T82	0	5	0	0
T84	0	13	0	0
T86	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T18
1	0	Covered	T1,T7,T82
1	1	Covered	T1,T7,T18

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	221546556	4683	0	0
g_div4.Div4Whole_A	221546556	5256	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546556	4683	0	0
T1	630827	90	0	0
T2	0	84	0	0
T5	9707	0	0	0
T6	3694	0	0	0
T7	1570	9	0	0
T8	1841	0	0	0
T18	791	2	0	0
T19	1096	0	0	0
T20	1259	0	0	0
T21	824	3	0	0
T22	1070	0	0	0
T64	0	2	0	0
T82	0	5	0	0
T84	0	13	0	0
T86	0	8	0	0
T107	0	5	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546556	5256	0	0
T1	630827	97	0	0
T2	0	91	0	0
T5	9707	0	0	0
T6	3694	0	0	0
T7	1570	9	0	0
T8	1841	0	0	0
T18	791	2	0	0
T19	1096	3	0	0
T20	1259	0	0	0
T21	824	3	0	0
T22	1070	0	0	0
T64	0	3	0	0
T82	0	4	0	0
T84	0	13	0	0
T86	0	12	0	0