Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	463040364	408	0	0
StatusRise_A	463040364	408	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463040364	408	0	0
T4	88791	0	0	0
T5	61041	0	0	0
T6	26454	0	0	0
T8	3372	15	0	0
T18	4506	0	0	0
T19	6780	0	0	0
T20	4476	16	0	0
T21	4758	0	0	0
T22	6822	0	0	0
T35	8583	0	0	0
T36	0	15	0	0
T165	0	5	0	0
T166	0	7	0	0
T167	0	7	0	0
T168	0	5	0	0
T169	0	4	0	0
T170	0	14	0	0
T171	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463040364	408	0	0
T4	88791	0	0	0
T5	61041	0	0	0
T6	26454	0	0	0
T8	3372	15	0	0
T18	4506	0	0	0
T19	6780	0	0	0
T20	4476	16	0	0
T21	4758	0	0	0
T22	6822	0	0	0
T35	8583	0	0	0
T36	0	15	0	0
T165	0	5	0	0
T166	0	7	0	0
T167	0	7	0	0
T168	0	5	0	0
T169	0	4	0	0
T170	0	14	0	0
T171	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154346788	135	0	0
StatusRise_A	154346788	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	135	0	0
T4	29597	0	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T8	1124	6	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	4	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T36	0	5	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	135	0	0
T4	29597	0	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T8	1124	6	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	4	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T36	0	5	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154346788	132	0	0
StatusRise_A	154346788	132	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	132	0	0
T4	29597	0	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T8	1124	5	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	6	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0
T171	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	132	0	0
T4	29597	0	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T8	1124	5	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	6	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0
T171	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154346788	141	0	0
StatusRise_A	154346788	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	141	0	0
T4	29597	0	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T8	1124	4	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	6	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T36	0	6	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154346788	141	0	0
T4	29597	0	0	0
T5	20347	0	0	0
T6	8818	0	0	0
T8	1124	4	0	0
T18	1502	0	0	0
T19	2260	0	0	0
T20	1492	6	0	0
T21	1586	0	0	0
T22	2274	0	0	0
T35	2861	0	0	0
T36	0	6	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0