Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48516	0	0
CgEnOn_A	2147483647	39153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48516	0	0
T1	2246698	453	0	0
T2	0	87	0	0
T4	504356	0	0	0
T5	219504	3	0	0
T6	125610	3	0	0
T7	18351	3	0	0
T8	42312	49	0	0
T18	17192	3	0	0
T19	25058	3	0	0
T20	29460	55	0	0
T21	18108	3	0	0
T22	25316	8	0	0
T35	13938	1	0	0
T36	0	25	0	0
T63	0	3	0	0
T83	0	3	0	0
T165	0	10	0	0
T166	0	10	0	0
T167	0	10	0	0
T168	0	10	0	0
T169	0	5	0	0
T170	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39153	0	0
T1	2246698	786	0	0
T2	0	931	0	0
T4	504356	0	0	0
T5	219504	0	0	0
T6	125610	0	0	0
T7	18351	0	0	0
T8	42312	84	0	0
T18	17192	0	0	0
T19	25058	0	0	0
T20	29460	84	0	0
T21	18108	0	0	0
T22	25316	17	0	0
T35	13938	8	0	0
T36	0	74	0	0
T63	0	10	0	0
T65	0	15	0	0
T83	0	31	0	0
T85	0	18	0	0
T109	0	4	0	0
T165	0	22	0	0
T166	0	18	0	0
T167	0	18	0	0
T168	0	14	0	0
T169	0	9	0	0
T170	0	32	0	0
T171	0	13	0	0
T172	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	221546152	135	0	0
CgEnOn_A	221546152	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546152	135	0	0
T2	0	1	0	0
T4	32049	0	0	0
T5	9706	0	0	0
T6	3694	0	0	0
T8	1840	5	0	0
T18	790	0	0	0
T19	1095	0	0	0
T20	1258	6	0	0
T21	823	0	0	0
T22	1070	0	0	0
T35	1433	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546152	135	0	0
T2	0	1	0	0
T4	32049	0	0	0
T5	9706	0	0	0
T6	3694	0	0	0
T8	1840	5	0	0
T18	790	0	0	0
T19	1095	0	0	0
T20	1258	6	0	0
T21	823	0	0	0
T22	1070	0	0	0
T35	1433	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	110772431	135	0	0
CgEnOn_A	110772431	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	135	0	0
T2	0	1	0	0
T4	16025	0	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	716	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	135	0	0
T2	0	1	0	0
T4	16025	0	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	716	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	110772431	135	0	0
CgEnOn_A	110772431	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	135	0	0
T2	0	1	0	0
T4	16025	0	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	716	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	135	0	0
T2	0	1	0	0
T4	16025	0	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	716	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	110772431	135	0	0
CgEnOn_A	110772431	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	135	0	0
T2	0	1	0	0
T4	16025	0	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	716	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	135	0	0
T2	0	1	0	0
T4	16025	0	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	716	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444527978	135	0	0
CgEnOn_A	444527978	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444527978	135	0	0
T2	0	1	0	0
T4	118388	0	0	0
T5	19533	0	0	0
T6	7467	0	0	0
T8	3718	5	0	0
T18	1517	0	0	0
T19	2236	0	0	0
T20	2568	6	0	0
T21	1603	0	0	0
T22	2274	0	0	0
T35	2890	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444527978	132	0	0
T4	118388	0	0	0
T5	19533	0	0	0
T6	7467	0	0	0
T8	3718	5	0	0
T18	1517	0	0	0
T19	2236	0	0	0
T20	2568	6	0	0
T21	1603	0	0	0
T22	2274	0	0	0
T35	2890	0	0	0
T36	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	3	0	0
T171	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473479621	139	0	0
CgEnOn_A	473479621	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	139	0	0
T4	123324	0	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	0	0	0
T35	3011	0	0	0
T36	0	5	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	135	0	0
T4	123324	0	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	0	0	0
T35	3011	0	0	0
T36	0	5	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473479621	139	0	0
CgEnOn_A	473479621	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	139	0	0
T4	123324	0	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	0	0	0
T35	3011	0	0	0
T36	0	5	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	135	0	0
T4	123324	0	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	0	0	0
T35	3011	0	0	0
T36	0	5	0	0
T165	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	6	0	0
T171	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Unreachable
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	227272248	143	0	0
CgEnOn_A	227272248	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227272248	143	0	0
T4	59196	0	0	0
T5	9766	0	0	0
T6	6613	0	0	0
T8	1950	4	0	0
T18	759	0	0	0
T19	1117	0	0	0
T20	1339	6	0	0
T21	801	0	0	0
T22	1137	0	0	0
T35	1445	0	0	0
T36	0	6	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227272248	141	0	0
T4	59196	0	0	0
T5	9766	0	0	0
T6	6613	0	0	0
T8	1950	4	0	0
T18	759	0	0	0
T19	1117	0	0	0
T20	1339	6	0	0
T21	801	0	0	0
T22	1137	0	0	0
T35	1445	0	0	0
T36	0	6	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T36
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	110772431	7799	0	0
CgEnOn_A	110772431	5467	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	7799	0	0
T1	315412	118	0	0
T5	4853	1	0	0
T6	1847	1	0	0
T7	783	1	0	0
T8	920	6	0	0
T18	395	1	0	0
T19	547	1	0	0
T20	629	7	0	0
T21	410	1	0	0
T22	535	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110772431	5467	0	0
T1	315412	107	0	0
T2	0	141	0	0
T5	4853	0	0	0
T6	1847	0	0	0
T7	783	0	0	0
T8	920	5	0	0
T18	395	0	0	0
T19	547	0	0	0
T20	629	6	0	0
T21	410	0	0	0
T22	535	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T65	0	3	0	0
T109	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T36
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	221546152	7849	0	0
CgEnOn_A	221546152	5517	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546152	7849	0	0
T1	630827	117	0	0
T5	9706	1	0	0
T6	3694	1	0	0
T7	1570	1	0	0
T8	1840	6	0	0
T18	790	1	0	0
T19	1095	1	0	0
T20	1258	7	0	0
T21	823	1	0	0
T22	1070	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221546152	5517	0	0
T1	630827	106	0	0
T2	0	146	0	0
T5	9706	0	0	0
T6	3694	0	0	0
T7	1570	0	0	0
T8	1840	5	0	0
T18	790	0	0	0
T19	1095	0	0	0
T20	1258	6	0	0
T21	823	0	0	0
T22	1070	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T65	0	4	0	0
T109	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T36
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444527978	7865	0	0
CgEnOn_A	444527978	5530	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444527978	7865	0	0
T1	126181	122	0	0
T5	19533	1	0	0
T6	7467	1	0	0
T7	2823	1	0	0
T8	3718	6	0	0
T18	1517	1	0	0
T19	2236	1	0	0
T20	2568	7	0	0
T21	1603	1	0	0
T22	2274	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444527978	5530	0	0
T1	126181	111	0	0
T2	0	143	0	0
T5	19533	0	0	0
T6	7467	0	0	0
T7	2823	0	0	0
T8	3718	5	0	0
T18	1517	0	0	0
T19	2236	0	0	0
T20	2568	6	0	0
T21	1603	0	0	0
T22	2274	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T65	0	3	0	0
T109	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T36
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	227272248	7826	0	0
CgEnOn_A	227272248	5491	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227272248	7826	0	0
T1	639866	121	0	0
T5	9766	1	0	0
T6	6613	1	0	0
T7	1411	1	0	0
T8	1950	5	0	0
T18	759	1	0	0
T19	1117	1	0	0
T20	1339	7	0	0
T21	801	1	0	0
T22	1137	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227272248	5491	0	0
T1	639866	110	0	0
T2	0	141	0	0
T5	9766	0	0	0
T6	6613	0	0	0
T7	1411	0	0	0
T8	1950	4	0	0
T18	759	0	0	0
T19	1117	0	0	0
T20	1339	6	0	0
T21	801	0	0	0
T22	1137	0	0	0
T35	0	1	0	0
T36	0	6	0	0
T65	0	5	0	0
T109	0	1	0	0
T165	0	1	0	0
T172	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Covered	T1,T22,T35
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473479621	3998	0	0
CgEnOn_A	473479621	3994	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	3998	0	0
T1	133603	96	0	0
T2	0	82	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	5	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	3	0	0
T83	0	3	0	0
T85	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	3994	0	0
T1	133603	96	0	0
T2	0	82	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	5	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	3	0	0
T83	0	3	0	0
T85	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Covered	T1,T22,T35
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473479621	3992	0	0
CgEnOn_A	473479621	3988	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	3992	0	0
T1	133603	80	0	0
T2	0	90	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	5	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	3	0	0
T83	0	8	0	0
T85	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	3988	0	0
T1	133603	80	0	0
T2	0	90	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	5	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	3	0	0
T83	0	8	0	0
T85	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Covered	T1,T22,T35
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473479621	4039	0	0
CgEnOn_A	473479621	4035	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	4039	0	0
T1	133603	87	0	0
T2	0	91	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	4	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	1	0	0
T83	0	11	0	0
T85	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	4035	0	0
T1	133603	87	0	0
T2	0	91	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	4	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	1	0	0
T83	0	11	0	0
T85	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T20
1	0	Covered	T1,T22,T35
1	1	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	473479621	4052	0	0
CgEnOn_A	473479621	4048	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	4052	0	0
T1	133603	89	0	0
T2	0	93	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	3	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	3	0	0
T83	0	9	0	0
T85	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473479621	4048	0	0
T1	133603	89	0	0
T2	0	93	0	0
T5	20347	0	0	0
T6	13779	0	0	0
T7	2941	0	0	0
T8	3936	6	0	0
T18	1580	0	0	0
T19	2329	0	0	0
T20	2769	4	0	0
T21	1669	0	0	0
T22	2369	3	0	0
T35	0	1	0	0
T36	0	5	0	0
T63	0	3	0	0
T83	0	9	0	0
T85	0	3	0	0