Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	601063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3352027

1

T5

19

T6

50

T7

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	969954	1			T5	17		T6	72		T7	42
values[0x0]	1371308	1			T5	15		T6	27		T7	19
values[0x1]	1611828	1			T5	20		T6	27		T7	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334528	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3618562

1

T5

23

T6

61

T7

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15706	1			T6	1		T1	6		T2	2
valid_sources[0x01]	15905	1			T5	52		T4	16		T2	3
valid_sources[0x02]	15252	1			T6	1		T7	2		T1	11
valid_sources[0x03]	15410	1			T1	20		T3	15		T10	452
valid_sources[0x04]	14758	1			T4	1		T2	1		T108	1
valid_sources[0x05]	15272	1			T1	24		T2	3		T3	8
valid_sources[0x06]	14443	1			T1	2		T19	1		T20	1
valid_sources[0x07]	14543	1			T6	2		T1	3		T93	2
valid_sources[0x08]	15204	1			T7	2		T1	1		T4	2
valid_sources[0x09]	14501	1			T6	1		T1	5		T111	1
valid_sources[0x0a]	16816	1			T1	8		T4	3		T2	2
valid_sources[0x0b]	14660	1			T6	1		T7	1		T1	26
valid_sources[0x0c]	16302	1			T1	5		T4	6		T3	10
valid_sources[0x0d]	16492	1			T6	1		T1	1		T4	2
valid_sources[0x0e]	16709	1			T6	2		T1	17		T4	14
valid_sources[0x0f]	15037	1			T1	10		T17	1		T2	2
valid_sources[0x10]	16600	1			T6	1		T1	4		T4	2
valid_sources[0x11]	16032	1			T1	14		T4	2		T2	2
valid_sources[0x12]	15027	1			T1	5		T4	9		T2	4
valid_sources[0x13]	17128	1			T6	1		T1	2		T4	7
valid_sources[0x14]	14737	1			T6	1		T1	12		T4	7
valid_sources[0x15]	16151	1			T1	3		T4	8		T111	2
valid_sources[0x16]	15035	1			T1	7		T4	14		T2	3
valid_sources[0x17]	12698	1			T24	31		T1	12		T2	2
valid_sources[0x18]	14355	1			T1	3		T4	21		T108	1
valid_sources[0x19]	15036	1			T6	2		T1	1		T4	1
valid_sources[0x1a]	15281	1			T2	1		T93	1		T108	3
valid_sources[0x1b]	16131	1			T1	20		T4	2		T2	2
valid_sources[0x1c]	15111	1			T1	8		T29	3		T3	9
valid_sources[0x1d]	15626	1			T6	1		T1	4		T4	4
valid_sources[0x1e]	15331	1			T1	7		T4	2		T2	1
valid_sources[0x1f]	13465	1			T7	1		T26	1		T1	24
valid_sources[0x20]	17503	1			T6	1		T26	1		T1	9
valid_sources[0x21]	15127	1			T1	18		T4	2		T2	3
valid_sources[0x22]	15345	1			T17	1		T93	1		T3	12
valid_sources[0x23]	15188	1			T7	1		T1	11		T4	34
valid_sources[0x24]	18211	1			T1	5		T4	9		T2	2
valid_sources[0x25]	16591	1			T6	1		T1	5		T2	2
valid_sources[0x26]	15267	1			T1	10		T2	1		T111	1
valid_sources[0x27]	15955	1			T1	2		T111	1		T3	5
valid_sources[0x28]	16210	1			T1	19		T2	2		T23	1
valid_sources[0x29]	16571	1			T6	1		T1	7		T4	16
valid_sources[0x2a]	16390	1			T7	1		T1	5		T2	1
valid_sources[0x2b]	15670	1			T1	20		T4	2		T2	1
valid_sources[0x2c]	16992	1			T1	13		T4	29		T2	1
valid_sources[0x2d]	14538	1			T7	4		T26	1		T1	1
valid_sources[0x2e]	17716	1			T6	1		T1	17		T4	15
valid_sources[0x2f]	13988	1			T1	13		T2	1		T23	1
valid_sources[0x30]	14738	1			T1	3		T4	1		T2	1
valid_sources[0x31]	15826	1			T6	1		T1	2		T4	8
valid_sources[0x32]	15198	1			T1	8		T4	2		T108	1
valid_sources[0x33]	15026	1			T25	6		T26	1		T1	8
valid_sources[0x34]	16714	1			T7	1		T1	1		T23	1
valid_sources[0x35]	14097	1			T6	1		T1	8		T93	3
valid_sources[0x36]	15891	1			T6	1		T7	1		T108	2
valid_sources[0x37]	15342	1			T1	3		T2	1		T19	1
valid_sources[0x38]	15476	1			T6	1		T1	14		T2	2
valid_sources[0x39]	15670	1			T1	29		T3	8		T10	461
valid_sources[0x3a]	15584	1			T6	1		T1	2		T4	3
valid_sources[0x3b]	12668	1			T6	1		T1	34		T19	1
valid_sources[0x3c]	15900	1			T26	1		T1	10		T22	2
valid_sources[0x3d]	16591	1			T6	1		T1	38		T20	1
valid_sources[0x3e]	15651	1			T1	4		T93	1		T108	1
valid_sources[0x3f]	16072	1			T1	12		T4	2		T3	6
valid_sources[0x40]	15288	1			T1	33		T3	12		T10	466
valid_sources[0x41]	14928	1			T1	16		T4	5		T2	4
valid_sources[0x42]	14875	1			T6	2		T7	1		T1	14
valid_sources[0x43]	15778	1			T1	1		T4	2		T2	1
valid_sources[0x44]	17110	1			T1	25		T4	9		T2	1
valid_sources[0x45]	15287	1			T6	1		T1	4		T2	1
valid_sources[0x46]	17359	1			T6	1		T1	30		T4	2
valid_sources[0x47]	15829	1			T1	9		T2	1		T108	1
valid_sources[0x48]	16337	1			T1	3		T3	6		T10	423
valid_sources[0x49]	14084	1			T6	3		T1	25		T20	1
valid_sources[0x4a]	14921	1			T7	2		T1	2		T2	6
valid_sources[0x4b]	15147	1			T1	4		T20	1		T3	5
valid_sources[0x4c]	16855	1			T1	3		T4	6		T2	3
valid_sources[0x4d]	14016	1			T1	14		T2	1		T3	12
valid_sources[0x4e]	16520	1			T6	2		T1	3		T2	3
valid_sources[0x4f]	14291	1			T6	2		T1	5		T4	17
valid_sources[0x50]	15251	1			T4	9		T2	1		T108	1
valid_sources[0x51]	15949	1			T7	1		T1	3		T2	2
valid_sources[0x52]	14645	1			T6	1		T1	11		T4	4
valid_sources[0x53]	15377	1			T6	1		T7	2		T1	7
valid_sources[0x54]	16046	1			T6	3		T1	2		T4	2
valid_sources[0x55]	14782	1			T1	5		T4	2		T2	1
valid_sources[0x56]	14717	1			T1	4		T2	3		T3	12
valid_sources[0x57]	15909	1			T6	1		T4	3		T3	6
valid_sources[0x58]	16875	1			T6	3		T7	2		T1	16
valid_sources[0x59]	14554	1			T6	1		T7	1		T1	6
valid_sources[0x5a]	14858	1			T7	2		T1	16		T3	8
valid_sources[0x5b]	15885	1			T1	1		T109	1		T111	4
valid_sources[0x5c]	13695	1			T1	14		T4	2		T2	1
valid_sources[0x5d]	15073	1			T7	1		T1	5		T2	7
valid_sources[0x5e]	15006	1			T7	1		T1	9		T2	1
valid_sources[0x5f]	15694	1			T1	31		T4	5		T29	3
valid_sources[0x60]	15513	1			T1	2		T93	1		T3	5
valid_sources[0x61]	14895	1			T7	2		T1	2		T19	1
valid_sources[0x62]	15165	1			T1	7		T3	11		T10	483
valid_sources[0x63]	14816	1			T1	23		T4	13		T2	4
valid_sources[0x64]	14386	1			T6	2		T1	1		T2	1
valid_sources[0x65]	15145	1			T1	6		T4	6		T2	3
valid_sources[0x66]	16100	1			T1	3		T2	2		T3	6
valid_sources[0x67]	14780	1			T6	1		T1	8		T2	3
valid_sources[0x68]	15007	1			T6	1		T1	7		T17	1
valid_sources[0x69]	15871	1			T7	1		T1	3		T4	13
valid_sources[0x6a]	16626	1			T1	3		T2	3		T29	3
valid_sources[0x6b]	14723	1			T6	1		T7	1		T1	3
valid_sources[0x6c]	14926	1			T1	10		T4	2		T3	5
valid_sources[0x6d]	13654	1			T1	5		T4	8		T2	1
valid_sources[0x6e]	15010	1			T1	8		T3	10		T10	463
valid_sources[0x6f]	15502	1			T6	1		T1	18		T20	1
valid_sources[0x70]	15368	1			T6	1		T1	26		T2	5
valid_sources[0x71]	13291	1			T1	19		T4	22		T19	3
valid_sources[0x72]	14663	1			T6	3		T1	7		T2	5
valid_sources[0x73]	16698	1			T1	7		T4	4		T20	1
valid_sources[0x74]	15820	1			T6	1		T1	7		T22	1
valid_sources[0x75]	16221	1			T1	17		T2	1		T3	3
valid_sources[0x76]	14418	1			T1	17		T2	1		T3	13
valid_sources[0x77]	15715	1			T1	1		T4	1		T2	1
valid_sources[0x78]	15261	1			T6	2		T1	12		T21	188
valid_sources[0x79]	14642	1			T1	6		T108	1		T111	1
valid_sources[0x7a]	13958	1			T1	5		T2	1		T108	1
valid_sources[0x7b]	14854	1			T7	3		T1	15		T2	1
valid_sources[0x7c]	16009	1			T1	2		T111	1		T3	2
valid_sources[0x7d]	15839	1			T1	11		T4	9		T23	1
valid_sources[0x7e]	16512	1			T1	18		T4	4		T2	2
valid_sources[0x7f]	14887	1			T6	1		T1	10		T2	3
valid_sources[0x80]	15870	1			T1	3		T4	6		T108	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

845545

1

T5

9

T6

38

T7

17

values[0x0]

all_enables

biggest_size

1276545

1

T5

4

T6

8

T7

3

values[0x1]

all_enables

biggest_size

1229937

1

T5

6

T6

4

T7

1