Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T4
0	1	Covered	T1,T97,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T4
1	0	Covered	T33,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1176532047	14923	0	0
GateOpen_A	1176532047	21718	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1176532047	14923	0	0
T1	1884838	85	0	0
T2	411358	0	0	0
T3	0	44	0	0
T4	260039	0	0	0
T7	3559	2	0	0
T10	0	188	0	0
T11	0	278	0	0
T12	0	77	0	0
T17	9607	0	0	0
T18	13579	0	0	0
T19	4682	0	0	0
T20	4351	0	0	0
T21	11912	0	0	0
T22	12019	0	0	0
T23	2901	0	0	0
T24	5568	0	0	0
T25	2336	0	0	0
T26	2358	0	0	0
T27	0	93	0	0
T97	0	5	0	0
T175	0	39	0	0
T176	0	19	0	0
T177	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1176532047	21718	0	0
T1	1884838	109	0	0
T2	411358	0	0	0
T4	260039	76	0	0
T5	16467	4	0	0
T6	20422	4	0	0
T7	5248	6	0	0
T17	9607	4	0	0
T20	0	4	0	0
T21	0	20	0	0
T23	0	4	0	0
T24	8529	4	0	0
T25	3446	0	0	0
T26	4472	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T21
0	1	Covered	T1,T97,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T33,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	129870923	3560	0	0
GateOpen_A	129870923	5257	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870923	3560	0	0
T1	202736	20	0	0
T2	45698	0	0	0
T3	0	8	0	0
T4	19440	0	0	0
T10	0	46	0	0
T11	0	59	0	0
T12	0	19	0	0
T17	1118	0	0	0
T18	1498	0	0	0
T19	519	0	0	0
T20	1450	0	0	0
T21	3970	0	0	0
T22	4006	0	0	0
T23	966	0	0	0
T27	0	22	0	0
T97	0	1	0	0
T175	0	10	0	0
T176	0	5	0	0
T177	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129870923	5257	0	0
T1	202736	26	0	0
T2	45698	0	0	0
T4	19440	19	0	0
T5	2022	1	0	0
T6	2263	1	0	0
T7	563	1	0	0
T17	1118	1	0	0
T20	0	1	0	0
T21	0	5	0	0
T23	0	1	0	0
T24	986	1	0	0
T25	370	0	0	0
T26	704	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T21
0	1	Covered	T1,T97,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T21
1	0	Covered	T33,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	259742680	3795	0	0
GateOpen_A	259742680	5492	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259742680	3795	0	0
T1	405481	23	0	0
T2	91395	0	0	0
T3	0	11	0	0
T4	38884	0	0	0
T10	0	45	0	0
T11	0	71	0	0
T12	0	20	0	0
T17	2236	0	0	0
T18	2995	0	0	0
T19	1039	0	0	0
T20	2901	0	0	0
T21	7942	0	0	0
T22	8013	0	0	0
T23	1935	0	0	0
T27	0	23	0	0
T97	0	1	0	0
T175	0	9	0	0
T176	0	5	0	0
T177	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259742680	5492	0	0
T1	405481	29	0	0
T2	91395	0	0	0
T4	38884	19	0	0
T5	4047	1	0	0
T6	4526	1	0	0
T7	1126	1	0	0
T17	2236	1	0	0
T20	0	1	0	0
T21	0	5	0	0
T23	0	1	0	0
T24	1975	1	0	0
T25	740	0	0	0
T26	1410	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T4
0	1	Covered	T1,T97,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T4
1	0	Covered	T33,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	520979680	3798	0	0
GateOpen_A	520979680	5498	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520979680	3798	0	0
T1	810747	20	0	0
T2	182841	0	0	0
T3	0	12	0	0
T4	134475	0	0	0
T7	2373	1	0	0
T10	0	48	0	0
T11	0	77	0	0
T12	0	19	0	0
T17	4168	0	0	0
T18	6057	0	0	0
T19	2083	0	0	0
T24	3712	0	0	0
T25	1557	0	0	0
T26	1572	0	0	0
T27	0	26	0	0
T97	0	1	0	0
T175	0	11	0	0
T176	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520979680	5498	0	0
T1	810747	26	0	0
T2	182841	0	0	0
T4	134475	19	0	0
T5	6932	1	0	0
T6	9089	1	0	0
T7	2373	2	0	0
T17	4168	1	0	0
T20	0	1	0	0
T21	0	5	0	0
T23	0	1	0	0
T24	3712	1	0	0
T25	1557	0	0	0
T26	1572	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T1,T4
0	1	Covered	T1,T97,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T4
1	0	Covered	T33,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	265938764	3770	0	0
GateOpen_A	265938764	5471	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265938764	3770	0	0
T1	465874	22	0	0
T2	91424	0	0	0
T3	0	13	0	0
T4	67240	0	0	0
T7	1186	1	0	0
T10	0	49	0	0
T11	0	71	0	0
T12	0	19	0	0
T17	2085	0	0	0
T18	3029	0	0	0
T19	1041	0	0	0
T24	1856	0	0	0
T25	779	0	0	0
T26	786	0	0	0
T27	0	22	0	0
T97	0	2	0	0
T175	0	9	0	0
T176	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	265938764	5471	0	0
T1	465874	28	0	0
T2	91424	0	0	0
T4	67240	19	0	0
T5	3466	1	0	0
T6	4544	1	0	0
T7	1186	2	0	0
T17	2085	1	0	0
T20	0	1	0	0
T21	0	5	0	0
T23	0	1	0	0
T24	1856	1	0	0
T25	779	0	0	0
T26	786	0	0	0