Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	764360580	75513	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764360580	75513	0	0
T1	2451375	181	0	0
T2	390455	195	0	0
T3	0	390	0	0
T4	119065	0	0	0
T10	0	1175	0	0
T11	0	2229	0	0
T12	0	285	0	0
T13	0	145	0	0
T14	0	116	0	0
T15	0	734	0	0
T16	0	895	0	0
T17	8030	0	0	0
T18	12305	0	0	0
T19	10845	0	0	0
T20	7095	0	0	0
T21	159160	0	0	0
T22	6450	0	0	0
T23	9815	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152872116	11115	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	11115	0	0
T1	490275	25	0	0
T2	78091	28	0	0
T3	0	53	0	0
T4	23813	0	0	0
T10	0	167	0	0
T11	0	315	0	0
T12	0	57	0	0
T13	0	23	0	0
T14	0	21	0	0
T15	0	96	0	0
T16	0	137	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T20	1419	0	0	0
T21	31832	0	0	0
T22	1290	0	0	0
T23	1963	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152872116	11115	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	11115	0	0
T1	490275	25	0	0
T2	78091	28	0	0
T3	0	49	0	0
T4	23813	0	0	0
T10	0	167	0	0
T11	0	310	0	0
T12	0	57	0	0
T13	0	23	0	0
T14	0	21	0	0
T15	0	107	0	0
T16	0	143	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T20	1419	0	0	0
T21	31832	0	0	0
T22	1290	0	0	0
T23	1963	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152872116	15235	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	15235	0	0
T1	490275	37	0	0
T2	78091	40	0	0
T3	0	78	0	0
T4	23813	0	0	0
T10	0	234	0	0
T11	0	501	0	0
T12	0	57	0	0
T13	0	29	0	0
T14	0	23	0	0
T15	0	141	0	0
T16	0	178	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T20	1419	0	0	0
T21	31832	0	0	0
T22	1290	0	0	0
T23	1963	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152872116	15111	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	15111	0	0
T1	490275	37	0	0
T2	78091	37	0	0
T3	0	77	0	0
T4	23813	0	0	0
T10	0	235	0	0
T11	0	435	0	0
T12	0	57	0	0
T13	0	30	0	0
T14	0	23	0	0
T15	0	147	0	0
T16	0	180	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T20	1419	0	0	0
T21	31832	0	0	0
T22	1290	0	0	0
T23	1963	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152872116	22937	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	22937	0	0
T1	490275	57	0	0
T2	78091	62	0	0
T3	0	133	0	0
T4	23813	0	0	0
T10	0	372	0	0
T11	0	668	0	0
T12	0	57	0	0
T13	0	40	0	0
T14	0	28	0	0
T15	0	243	0	0
T16	0	257	0	0
T17	1606	0	0	0
T18	2461	0	0	0
T19	2169	0	0	0
T20	1419	0	0	0
T21	31832	0	0	0
T22	1290	0	0	0
T23	1963	0	0	0