Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T4,T21

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	152872116	150257726	0	0
AllClkBypReqTrue_A	152872116	140733	0	0
IoClkBypReqFalse_A	152872116	150173994	0	2412
IoClkBypReqTrue_A	152872116	219671	0	0
LcClkBypAckFalse_A	152872116	150266493	0	0
LcClkBypAckTrue_A	152872116	131966	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	150257726	0	0
T1	490275	488751	0	0
T2	78091	78039	0	0
T4	23813	3294	0	0
T5	2527	2008	0	0
T6	2366	2341	0	0
T7	2397	2163	0	0
T17	1606	1395	0	0
T24	1895	1528	0	0
T25	1477	1270	0	0
T26	1636	1462	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	140733	0	0
T1	490275	386	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	489	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	127	0	0
T19	0	38	0	0
T20	0	62	0	0
T22	0	69	0	0
T23	0	140	0	0
T24	1895	234	0	0
T25	1477	0	0	0
T26	1636	76	0	0
T62	0	24	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	150173994	0	2412
T1	490275	488374	0	3
T2	78091	78037	0	3
T4	23813	3256	0	3
T5	2527	1920	0	3
T6	2366	2339	0	3
T7	2397	2161	0	3
T17	1606	1265	0	3
T24	1895	1498	0	3
T25	1477	1268	0	3
T26	1636	1499	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	219671	0	0
T1	490275	737	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	575	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	255	0	0
T19	0	315	0	0
T22	0	24	0	0
T24	1895	262	0	0
T25	1477	0	0	0
T26	1636	37	0	0
T62	0	170	0	0
T93	0	187	0	0
T108	0	561	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	150266493	0	0
T1	490275	488679	0	0
T2	78091	78039	0	0
T4	23813	3294	0	0
T5	2527	2120	0	0
T6	2366	2341	0	0
T7	2397	2163	0	0
T17	1606	1431	0	0
T24	1895	1604	0	0
T25	1477	1270	0	0
T26	1636	1512	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152872116	131966	0	0
T1	490275	458	0	0
T2	78091	0	0	0
T4	23813	0	0	0
T5	2527	377	0	0
T6	2366	0	0	0
T7	2397	0	0	0
T17	1606	91	0	0
T19	0	74	0	0
T24	1895	158	0	0
T25	1477	0	0	0
T26	1636	26	0	0
T62	0	89	0	0
T93	0	86	0	0
T108	0	263	0	0
T109	0	29	0	0